Preliminary Datasheet ADSP-21562, ADSP-21563, ADSP-21565 (Analog Devices) - 14

ADSP-21562/21563/21565 Preliminary Technical Data
in functionality and operate independently of each other. The
Octal Serial Peripheral Interface (OSPI) Port
two signals generated by each unit are normally used as a serial The octal serial peripheral interface (OSPI) port provides an bit clock/frame sync pair. increased external memory data bus width (up to 8 bits in paral-
Universal Asynchronous Receiver/Transmitter
lel). The OSPI port supports DDR modes of operation, which
(UART) Ports
enable the transfer of up to 16 bits of data in each clock. The OSPI port provides overall data throughput and performance The processors provide full-duplex universal asynchronous improvement, including faster boot time. receiver/transmitter (UART) ports, fully compatible with PC standard UARTs. Each UART port provides a simplified UART Feature of the OSPI port include: interface to other peripherals or hosts, supporting full-duplex, • Support for single, dual, quad, or octal I/O transfers DMA supported, asynchronous transfers of serial data. A UART • Multiple modes of operation including direct and STIG port includes support for five to eight data bits as well as no par- (software triggered instruction generator) ity, even parity, or odd parity. • Support for XIP (execute in place): continuous mode Optionally, an additional address bit can be transferred to inter- rupt only addressed nodes in multidrop bus (MDB) systems. A • Programmable page and block sizes frame is terminated by a configurable number of stop bits. • Programmable write protected regions The UART ports support automatic hardware flow control • Programmable memory timing through the clear to send (CTS) input and request to send (RTS) • Support for DDR commands output with programmable assertion first in, first out (FIFO) levels.
Link Port (LP)
To help support the Local Interconnect Network (LIN) proto- Two 8-bit wide link ports (LP) for the BGA package can connect cols, a special command causes the transmitter to queue a break to the link ports of other DSPs or peripherals. Link ports are command of programmable bit length into the transmit buffer. bidirectional and have eight data lines, an acknowledge line, and Similarly, the number of stop bits can be extended by a pro- a clock line. grammable interframe space.
Timers Serial Peripheral Interface (SPI) Ports
The processors include several timers that are described in the The processors have four industry-standard SPI-compatible following sections. ports that allow the processors to communicate with multiple SPI-compatible devices.
General-Purpose (GP) Timers (TIMER)
The baseline SPI peripheral is a synchronous, 4-wire interface There is one general-purpose (GP) timer unit, providing ten consisting of two data pins, one device select pin, and a gated general-purpose programmable timers. Each timer has an exter- clock pin. The two data pins allow full-duplex operation to nal pin that can be configured either as PWM or timer output, other SPI-compatible devices. An extra two (optional) data pins as an input to clock the timer, or as a mechanism for measuring are provided to support quad-SPI operation. Enhanced modes pulse widths and periods of external events. These timers can be of operation, such as flow control, fast mode, and dual-I/O synchronized to an external clock input on the TM_TMR[n] mode (DIOM), are also supported. DMA mode allows for trans- pins, an external TM_CLK input pin, or to the internal SCLK0. ferring several words with minimal central processing unit These timer units can be used in conjunction with the UARTs to (CPU) interaction. measure the width of the pulses in the data stream to provide a With a range of configurable options, the SPI ports provide a software autobaud detect function for the respective serial glueless hardware interface with other SPI-compatible devices channels. in master mode, slave mode, and multimaster environments. The GP timers can generate interrupts to the processor core, The SPI peripheral includes programmable baud rates, clock providing periodic events for synchronization to either the sys- phase, and clock polarity. The peripheral can operate in a tem clock or to external signals. Timer events can also trigger multimaster environment by interfacing with several other other peripherals via the TRU (for instance, to signal a fault). devices, acting as either a master device or a slave device. In a Each timer can also be started and/or stopped by any TRU mas- multimaster environment, the SPI peripheral uses open-drain ter without core intervention. outputs to avoid data bus contention. The flow control features enable slow slave devices to interface with fast master devices by
Watchdog Timer (WDT)
providing an SPI ready pin (SPI_RDY) which flexibly controls Two on-chip software watchdog timers (WDT) can be used by the transfers. the SHARC+ core. A software watchdog can improve system The baud rate and clock phase and polarities of the SPI port are availability by forcing the processors to a known state, via a gen- programmable. The port has integrated DMA channels for both eral-purpose interrupt, or a fault, if the timer expires before transmit and receive data streams. being reset by software. Rev. PrG | Page 14 of 95 | June 2020 Document Outline System Features Memory Additional Features Applications Table of Contents Revision History General Description SHARC Processor L1 Memory L1 Master and Slave Ports L1 On-Chip Memory Bandwidth Instruction and Data Cache System Event Controller (SEC) Input Core Memory-Mapped Registers (CMMR) SHARC+ Core Architecture Single-Instruction, Multiple Data (SIMD) Computational Engine Independent Parallel Computation Units Core Timer Data Register File Context Switch Universal Registers Data Address Generators (DAG) With Zero-Overhead Hardware Circular Buffer Support Flexible Instruction Set Architecture (ISA) Variable Instruction Set Architecture (VISA) Single-Cycle Fetch of Instructional Four Operands Core Event Controller (CEC) Instruction Conflict Cache Branch Target Buffer (BTB)/Branch Predictor (BP) Addressing Spaces Additional Features System Infrastructure System L2 Memory One Time Programmable Memory (OTP) I/O Memory Space System Memory Map System Crossbars (SCBs) Direct Memory Access (DMA) Memory Direct Memory Access (MDMA) Extended Memory DMA Cyclic Redundant Code (CRC) Protection Event Handling System Event Controller (SEC) Trigger Routing Unit (TRU) Security Features Cryptographic Hardware Accelerators System Protection Unit (SPU) System Memory Protection Unit (SMPU) Security Features Disclaimer Safety Features Multiparity Bit Protected SHARC+ Core L1 Memories Error Correcting Codes (ECC) Protected L2 Memories Parity-Protected Peripheral Memories Cyclic Redundant Code (CRC) Protected Memories Signal Watchdogs System Event Controller (SEC) Memory Error Controller (MEC) Processor Peripherals Dynamic Memory Controller (DMC) Digital Audio Interface (DAI) Serial Port (SPORT) Asynchronous Sample Rate Converter (ASRC) S/PDIF-Compatible Digital Audio Receiver/Transmitter Precision Clock Generators (PCG) Universal Asynchronous Receiver/Transmitter (UART) Ports Serial Peripheral Interface (SPI) Ports Octal Serial Peripheral Interface (OSPI) Port Link Port (LP) Timers General-Purpose (GP) Timers (TIMER) Watchdog Timer (WDT) General-Purpose Counters (CNT) Media Local Bus (MediaLB) 2-Wire Controller Interface (TWI) General-Purpose I/O (GPIO) Pin Interrupts System Acceleration Finite Impulse Response (FIR) Accelerator Infinite Impulse Response (IIR) Accelerator System Design Clock Management Reset Control Unit (RCU) Clock Generation Unit (CGU) System Crystal Oscillator Clock Distribution Unit (CDU) Clock Out/External Clock Booting Power Supplies Power Management Power-Up and Power-Down Sequencing Target Board JTAG Emulator Connector System Debug System Watchpoint Unit (SWU) Debug Access Port (DAP) Development Tools Integrated Development Environments (IDEs) EZ-KIT Evaluation Board EZ-KIT Evaluation Kits Software Add Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains ADSP-2156x Detailed Signal Descriptions 400-Ball CSP_BGA Signal Descriptions GPIO Multiplexing for 400-Ball CSP_BGA Package 120-Lead LQFP Signal Descriptions GPIO Multiplexing for 120-Lead LQFP ADSP-2156x Designer Quick Reference Preliminary Specifications Preliminary Operating Conditions Preliminary Clock Related Operating Conditions Preliminary Electrical Characteristics Absolute Maximum Ratings ESD Caution Timing Specifications Power-Up Reset Timing Clock and Reset Timing Link Ports (LPs) Serial Ports (SPORTs) Asynchronous Sample Rate Converter (ASRC)—Serial Input Port Asynchronous Sample Rate Converter (ASRC)—Serial Output Port SPI Port—Master Timing SPI0, SPI1, and SPI2 SPI Port—Slave Timing SPI0, SPI1, and SPI2 SPI Port—SPIx_RDY Slave Timing SPI Port—Open Drain Mode (ODM) Timing SPI Port—SPIx_RDY Master Timing OSPI Port—Master Timing OSPI0 Precision Clock Generator (PCG) (Direct Pin Routing) General-Purpose IO Port Timing General-Purpose I/O Timer Cycle Timing DAIx Pin to DAIx Pin Direct Routing (DAI0 Block and DAI1 Block) Up/Down Counter/Rotary Encoder Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing Sony/Philips Digital Interface (S/PDIF) Transmitter S/PDIF Transmitter Serial Input Waveforms S/PDIF Transmitter Input Data Timing Oversampling Clock (TxCLK) Switching Characteristics S/PDIF Receiver Internal Digital PLL Mode MediaLB (MLB) Program Trace Macrocell (PTM) Timing Debug Interface (JTAG Emulation Port) Timing ADSP-2156x 400-Ball BGA Ball Assignments ADSP-2156x 400-Ball BGA Ball Assignments (Numerical by Ball Number) ADSP-2156x 400-Ball BGA Ball Assignments (Alphabetical by Pin Name) Configuration of the 400-Ball CSP_BGA ADSP-2156x 120-Lead LQFP Lead Assignments ADSP-2156x 120-Lead LQFP Lead Assignments (Numerical by Lead Number) ADSP-2156x 120-Lead LQFP Lead Assignments (Alphabetical by Pin Name) Configuration of the 120-Lead LQFP Lead Configuration Outline Dimensions Surface-Mount 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