Datasheet ADSP-21483, ADSP-21486, ADSP-21487, ADSP-21488, ADSP-21489 (Analog Devices) - 16
| Manufacturer | Analog Devices |
| Description | SHARC Processor |
| Pages / Page | 71 / 16 — ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489. Table 11. Pin … |
| Revision | H |
| File Format / Size | PDF / 1.9 Mb |
| Document Language | English |
ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489. Table 11. Pin Descriptions (Continued). State During/. Name. Type
Model Line for this Datasheet
Text Version of Document
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ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 Table 11. Pin Descriptions (Continued) State During/ Name Type After Reset Description
MLBCLK1 I
Media Local Bus Clock.
This clock is generated by the MLB controller that is synchro- nized to the MOST network and provides the timing for the entire MLB interface at 49.152 MHz at FS=48 kHz. When the MLB controller is not used, this pin should be grounded. MLBDAT1 I/O/T in 3 High-Z
Media Local Bus Data.
The MLBDAT line is driven by the transmitting MLB device and pin mode. I is received by all other MLB devices including the MLB controller. The MLBDAT line in 5 pin carries the actual data. In 5-pin MLB mode, this pin is an input only. When the MLB mode. controller is not used, this pin should be grounded. MLBSIG1 I/O/T in 3 High-Z
Media Local Bus Signal.
This is a multiplexed signal which carries the Channel/Address pin mode. I generated by the MLB Controller, as well as the Command and RxStatus bytes from in 5 pin MLB devices. In 5-pin mode, this pin is input only. When the MLB controller is not used, mode this pin should be grounded. MLBDO1 O/T High-Z
Media Local Bus Data Output (in 5 pin mode).
This pin is used only in 5-pin MLB mode. This serves as the output data pin in 5-pin mode. When the MLB controller is not used, this pin should be connected to ground. MLBSO1 O/T High-Z
Media Local Bus Signal Output (in 5 pin mode).
This pin is used only in 5-pin MLB mode. This serves as the output signal pin in 5-pin mode. When the MLB controller is not used, this pin should be connected to ground. TDI I (ipu)
Test Data Input (JTAG).
Provides serial data for the boundary scan logic. TDO O/T High-Z
Test Data Output (JTAG).
Serial scan output of the boundary scan path. TMS I (ipu)
Test Mode Select (JTAG).
Used to control the test state machine. TCK I
Test Clock (JTAG).
Provides a clock for JTAG boundary scan. TCK must be asserted (pulsed low) after power-up or held low for proper operation of the device. TRST I (ipu)
Test Reset (JTAG).
Resets the test state machine. TRST must be asserted (pulsed low) after power-up or held low for proper operation of the processor. EMU O (O/D, ipu) High-Z
Emulation Status.
Must be connected to the ADSP-2148x Analog Devices DSP Tools product line of JTAG emulators target board connector only. The following symbols appear in the Type column of this table:
A
= asynchronous,
I
= input,
O
= output,
S
= synchronous,
A/D
= active drive,
O/D
= open drain, and
T
= three-state,
ipd
= internal pull-down resistor,
ipu
= internal pull-up resistor. The internal pull-up (ipu) and internal pull-down (ipd) resistors are designed to hold the internal path from the pins at the expected logic levels. To pull-up or pull-down the external pads to the expected logic levels, use external resistors. Internal pull-up/pull-down resistors cannot be enabled/disabled and the value of these resistors cannot be programmed. The range of an ipu resistor can be between 26 kΩ–63 kΩ. The range of an ipd resistor can be between 31 kΩ–85 kΩ. The three-state voltage of ipu pads will not reach to the full VDD_EXT level; at typical conditions the voltage is in the range of 2.3 V to 2.7 V. In this table, all pins are LVTTL compliant with the exception of the thermal diode pins. Rev. H | Page 16 of 71 | February 2020 Document Outline Features Table of Contents Revision History General Description Family Core Architecture SIMD Computational Engine Independent, Parallel Computation Units Timer Data Register File Context Switch Universal Registers Single-Cycle Fetch of Instruction and Four Operands Instruction Cache Data Address Generators With Zero-Overhead Hardware Circular Buffer Support Flexible Instruction Set Variable Instruction Set Architecture (VISA) On-Chip Memory ROM Based Security On-Chip Memory Bandwidth Family Peripheral Architecture External Memory External Port Asynchronous Memory Controller SDRAM Controller SIMD Access to External Memory VISA and ISA Access to External Memory Pulse-Width Modulation MediaLB Digital Applications Interface (DAI) Serial Ports (SPORTs) S/PDIF-Compatible Digital Audio Receiver/Transmitter Asynchronous Sample Rate Converter (SRC) Input Data Port Precision Clock Generators Digital Peripheral Interface (DPI) Serial Peripheral (Compatible) Interface (SPI) UART Port Timers 2-Wire Interface Port (TWI) I/O Processor Features DMA Controller Delay Line DMA Scatter/Gather DMA FFT Accelerator FIR Accelerator IIR Accelerator Watchdog Timer System Design Program Booting Power Supplies Static Voltage Scaling (SVS) Target Board JTAG Emulator Connector Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Function Descriptions Specifications Operating Conditions Electrical Characteristics Total Power Dissipation Absolute Maximum Ratings ESD Sensitivity Maximum Power Dissipation Timing Specifications Core Clock Requirements Voltage Controlled Oscillator (VCO) Power-Up Sequencing Clock Input Clock Signals Reset Running Reset Interrupts Core Timer Timer PWM_OUT Cycle Timing Timer WDTH_CAP Timing Watchdog Timer Timing Pin to Pin Direct Routing (DAI and DPI) Precision Clock Generator (Direct Pin Routing) Flags SDRAM Interface Timing (166 MHz SDCLK) AMI Read AMI Write Serial Ports Input Data Port (IDP) Parallel Data Acquisition Port (PDAP) Sample Rate Converter—Serial Input Port Sample Rate Converter—Serial Output Port Pulse-Width Modulation Generators (PWM) S/PDIF Transmitter S/PDIF Transmitter-Serial Input Waveforms S/PDIF Transmitter Input Data Timing Oversampling Clock (TxCLK) Switching Characteristics S/PDIF Receiver Internal Digital PLL Mode SPI Interface—Master SPI Interface—Slave Media Local Bus Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing 2-Wire Interface (TWI)—Receive and Transmit Timing JTAG Test Access Port and Emulation Output Drive Currents Test Conditions Capacitive Loading Thermal Characteristics Thermal Diode 88-Lead LFCSP_VQ Lead Assignment 100-Lead LQFP_EP Lead Assignment 176-Lead LQFP_EP Lead Assignment Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide
ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 Table 11. Pin Descriptions (Continued) State During/ Name Type After Reset Description
MLBCLK1 I
Media Local Bus Clock.
This clock is generated by the MLB controller that is synchro- nized to the MOST network and provides the timing for the entire MLB interface at 49.152 MHz at FS=48 kHz. When the MLB controller is not used, this pin should be grounded. MLBDAT1 I/O/T in 3 High-Z
Media Local Bus Data.
The MLBDAT line is driven by the transmitting MLB device and pin mode. I is received by all other MLB devices including the MLB controller. The MLBDAT line in 5 pin carries the actual data. In 5-pin MLB mode, this pin is an input only. When the MLB mode. controller is not used, this pin should be grounded. MLBSIG1 I/O/T in 3 High-Z
Media Local Bus Signal.
This is a multiplexed signal which carries the Channel/Address pin mode. I generated by the MLB Controller, as well as the Command and RxStatus bytes from in 5 pin MLB devices. In 5-pin mode, this pin is input only. When the MLB controller is not used, mode this pin should be grounded. MLBDO1 O/T High-Z
Media Local Bus Data Output (in 5 pin mode).
This pin is used only in 5-pin MLB mode. This serves as the output data pin in 5-pin mode. When the MLB controller is not used, this pin should be connected to ground. MLBSO1 O/T High-Z
Media Local Bus Signal Output (in 5 pin mode).
This pin is used only in 5-pin MLB mode. This serves as the output signal pin in 5-pin mode. When the MLB controller is not used, this pin should be connected to ground. TDI I (ipu)
Test Data Input (JTAG).
Provides serial data for the boundary scan logic. TDO O/T High-Z
Test Data Output (JTAG).
Serial scan output of the boundary scan path. TMS I (ipu)
Test Mode Select (JTAG).
Used to control the test state machine. TCK I
Test Clock (JTAG).
Provides a clock for JTAG boundary scan. TCK must be asserted (pulsed low) after power-up or held low for proper operation of the device. TRST I (ipu)
Test Reset (JTAG).
Resets the test state machine. TRST must be asserted (pulsed low) after power-up or held low for proper operation of the processor. EMU O (O/D, ipu) High-Z
Emulation Status.
Must be connected to the ADSP-2148x Analog Devices DSP Tools product line of JTAG emulators target board connector only. The following symbols appear in the Type column of this table:
A
= asynchronous,
I
= input,
O
= output,
S
= synchronous,
A/D
= active drive,
O/D
= open drain, and
T
= three-state,
ipd
= internal pull-down resistor,
ipu
= internal pull-up resistor. The internal pull-up (ipu) and internal pull-down (ipd) resistors are designed to hold the internal path from the pins at the expected logic levels. To pull-up or pull-down the external pads to the expected logic levels, use external resistors. Internal pull-up/pull-down resistors cannot be enabled/disabled and the value of these resistors cannot be programmed. The range of an ipu resistor can be between 26 kΩ–63 kΩ. The range of an ipd resistor can be between 31 kΩ–85 kΩ. The three-state voltage of ipu pads will not reach to the full VDD_EXT level; at typical conditions the voltage is in the range of 2.3 V to 2.7 V. In this table, all pins are LVTTL compliant with the exception of the thermal diode pins. Rev. H | Page 16 of 71 | February 2020 Document Outline Features Table of Contents Revision History General Description Family Core Architecture SIMD Computational Engine Independent, Parallel Computation Units Timer Data Register File Context Switch Universal Registers Single-Cycle Fetch of Instruction and Four Operands Instruction Cache Data Address Generators With Zero-Overhead Hardware Circular Buffer Support Flexible Instruction Set Variable Instruction Set Architecture (VISA) On-Chip Memory ROM Based Security On-Chip Memory Bandwidth Family Peripheral Architecture External Memory External Port Asynchronous Memory Controller SDRAM Controller SIMD Access to External Memory VISA and ISA Access to External Memory Pulse-Width Modulation MediaLB Digital Applications Interface (DAI) Serial Ports (SPORTs) S/PDIF-Compatible Digital Audio Receiver/Transmitter Asynchronous Sample Rate Converter (SRC) Input Data Port Precision Clock Generators Digital Peripheral Interface (DPI) Serial Peripheral (Compatible) Interface (SPI) UART Port Timers 2-Wire Interface Port (TWI) I/O Processor Features DMA Controller Delay Line DMA Scatter/Gather DMA FFT Accelerator FIR Accelerator IIR Accelerator Watchdog Timer System Design Program Booting Power Supplies Static Voltage Scaling (SVS) Target Board JTAG Emulator Connector Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Function Descriptions Specifications Operating Conditions Electrical Characteristics Total Power Dissipation Absolute Maximum Ratings ESD Sensitivity Maximum Power Dissipation Timing Specifications Core Clock Requirements Voltage Controlled Oscillator (VCO) Power-Up Sequencing Clock Input Clock Signals Reset Running Reset Interrupts Core Timer Timer PWM_OUT Cycle Timing Timer WDTH_CAP Timing Watchdog Timer Timing Pin to Pin Direct Routing (DAI and DPI) Precision Clock Generator (Direct Pin Routing) Flags SDRAM Interface Timing (166 MHz SDCLK) AMI Read AMI Write Serial Ports Input Data Port (IDP) Parallel Data Acquisition Port (PDAP) Sample Rate Converter—Serial Input Port Sample Rate Converter—Serial Output Port Pulse-Width Modulation Generators (PWM) S/PDIF Transmitter S/PDIF Transmitter-Serial Input Waveforms S/PDIF Transmitter Input Data Timing Oversampling Clock (TxCLK) Switching Characteristics S/PDIF Receiver Internal Digital PLL Mode SPI Interface—Master SPI Interface—Slave Media Local Bus Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing 2-Wire Interface (TWI)—Receive and Transmit Timing JTAG Test Access Port and Emulation Output Drive Currents Test Conditions Capacitive Loading Thermal Characteristics Thermal Diode 88-Lead LFCSP_VQ Lead Assignment 100-Lead LQFP_EP Lead Assignment 176-Lead LQFP_EP Lead Assignment Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide