Datasheet ADSP-21369 (Analog Devices) - 3
| Manufacturer | Analog Devices |
| Description | SHARC Processor |
| Pages / Page | 60 / 3 — ADSP-21369. GENERAL DESCRIPTION. Table 2. Product Features (Continued). … |
| Revision | H |
| File Format / Size | PDF / 1.7 Mb |
| Document Language | English |
ADSP-21369. GENERAL DESCRIPTION. Table 2. Product Features (Continued). Feature. Table 1. Processor Benchmarks (at 400 MHz)
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ADSP-21369 GENERAL DESCRIPTION
The ADSP-21369 SHARC® processor is a member of the SIMD
Table 2. Product Features (Continued)
SHARC family of DSPs that feature Analog Devices’ Super Har- vard Architecture. These processors are source code-compatible
Feature ADSP-21369
with the ADSP-2126x and ADSP-2116x DSPs as well as with DPI Yes first generation ADSP-2106x SHARC processors in SISD (sin- gle-instruction, single-data) mode. The processors are 32- S/PDIF Transceiver 1 bit/40-bit floating-point processors optimized for high perfor- AMI Interface Bus Width 32 bits/16 bits/8 bits mance automotive audio applications with its large on-chip SRAM, mask programmable ROM, multiple internal buses to SPI 2 eliminate I/O bottlenecks, and an innovative digital applications TWI Yes interface (DAI). SRC Performance 128 dB As shown in the functional block diagram on Page 1, the processor uses two computational units to deliver a significant Shared Memory Support 256-Ball BGA only performance increase over the previous SHARC processors on a Package 256-Ball BGA, 208-Lead LQFP_EP range of DSP algorithms. Fabricated in a state-of-the-art, high speed, CMOS process, the processor achieves an instruction cycle time of up to 2.5 ns at 400 MHz. With its SIMD computa- The diagram on Page 1 shows the two clock domains. The core tional hardware, the processor can perform 2.4 GFLOPS clock domain contains the following features. running at 400 MHz. • Two processing elements (PEx, PEy), each of which com- Table 1 shows performance benchmarks for the ADSP-21369 prises an ALU, multiplier, shifter, and data register file processor. • Data address generators (DAG1, DAG2) • Program sequencer with instruction cache
Table 1. Processor Benchmarks (at 400 MHz)
• PM and DM buses capable of supporting two 64-bit data
Speed
transfers between memory and the core at every core pro-
Benchmark Algorithm (at 400 MHz)
cessor cycle 1024 Point Complex FFT (Radix 4, with Reversal) 23.2 s • One periodic interval timer with pinout FIR Filter (per Tap)1 1.25 ns • On-chip SRAM (2M bit) IIR Filter (per Biquad)1 5.0 ns • JTAG test access port for emulation and boundary scan. Matrix Multiply (Pipelined) The JTAG provides software debug through user break- [3×3] × [3×1] 11.25 ns points which allows flexible exception handling. [4×4] × [4×1] 20.0 ns The block diagram on Page 1 also shows the peripheral clock Divide (y/x) 8.75 ns domain (also known as the I/O processor) and contains the fol- Inverse Square Root 13.5 ns lowing features: 1 Assumes two files in multichannel SIMD mode. • IOD0 (periphera l DMA) and IOD1 (external port DMA) buses for 32-bit data transfers
Table 2. Product Features
• Peripheral and external port buses for core connection • External port with an AMI and SDRAM controller
Feature ADSP-21369
• 4 units for PWM control Frequency 400 MHz • 1 MTM unit for internal-to-internal memory transfers RAM 2M bits • Digital applications interface that includes four precision ROM 6M bits clock generators (PCG), a input data port (IDP) for serial Pulse-Width Modulation Yes and parallel interconnect, an S/PDIF receiver/transmitter, four asynchronous sample rate converters, eight serial S/PDIF Yes ports, a flexible signal routing unit (DAI SRU). SDRAM Memory Bus Width 32 bits/16 bits • Digital peripheral interface that includes three timers, a 2- Serial Ports 8 wire interface, two UARTs, two serial peripheral interfaces (SPI), 2 precision clock generators (PCG) and a flexible sig- IDP Yes nal routing unit (DPI SRU). DAI Yes UART 2 Rev. H | Page 3 of 60 | March 2019 Document Outline Summary Dedicated Audio Components Table of Contents Revision History General Description SHARC Family Core Architecture SIMD Computational Engine Independent, Parallel Computation Units Data Register File Context Switch Universal Registers Timer Single-Cycle Fetch of Instruction and Four Operands Instruction Cache Data Address Generators with Zero-Overhead Hardware Circular Buffer Support Flexible Instruction Set On-Chip Memory On-Chip Memory Bandwidth ROM-Based Security Family Peripheral Architecture External Port SDRAM Controller External Memory Shared External Memory External Port Throughput Asynchronous Memory Controller Pulse-Width Modulation Digital Applications Interface (DAI) Serial Ports S/PDIF-Compatible Digital Audio Receiver/Transmitter Synchronous/Asynchronous Sample Rate Converter Input Data Port Precision Clock Generators Digital Peripheral Interface (DPI) Serial Peripheral (Compatible) Interface UART Port Peripheral Timers 2-Wire Interface Port (TWI) I/O Processor Features DMA Controller Delay Line DMA System Design Program Booting Power Supplies Target Board JTAG Emulator Connector Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Function Descriptions Specifications Operating Conditions Electrical Characteristics ESD Caution Maximum Power Dissipation Absolute Maximum Ratings Timing Specifications Core Clock Requirements Voltage Controlled Oscillator Power-Up Sequencing Clock Input Clock Signals Reset Interrupts Core Timer Timer PWM_OUT Cycle Timing Timer WDTH_CAP Timing Pin to Pin Direct Routing (DAI and DPI) Precision Clock Generator (Direct Pin Routing) Flags SDRAM Interface Timing (166 MHz SDCLK) SDRAM Interface Enable/Disable Timing (166 MHz SDCLK) Memory Read Memory Write Asynchronous Memory Interface (AMI) Enable/Disable Shared Memory Bus Request Serial Ports Input Data Port Parallel Data Acquisition Port (PDAP) Pulse-Width Modulation Generators Sample Rate Converter—Serial Input Port Sample Rate Converter—Serial Output Port S/PDIF Transmitter S/PDIF Transmitter—Serial Input Waveforms S/PDIF Transmitter Input Data Timing Oversampling Clock (TxCLK) Switching Characteristics S/PDIF Receiver Internal Digital PLL Mode SPI Interface—Master SPI Interface—Slave JTAG Test Access Port and Emulation Output Drive Currents Test Conditions Capacitive Loading Thermal Characteristics 256-Ball BGA_ED Pinout 208-Lead LQFP_EP Pinout Package Dimensions Surface-Mount Design Ordering Guide
ADSP-21369 GENERAL DESCRIPTION
The ADSP-21369 SHARC® processor is a member of the SIMD
Table 2. Product Features (Continued)
SHARC family of DSPs that feature Analog Devices’ Super Har- vard Architecture. These processors are source code-compatible
Feature ADSP-21369
with the ADSP-2126x and ADSP-2116x DSPs as well as with DPI Yes first generation ADSP-2106x SHARC processors in SISD (sin- gle-instruction, single-data) mode. The processors are 32- S/PDIF Transceiver 1 bit/40-bit floating-point processors optimized for high perfor- AMI Interface Bus Width 32 bits/16 bits/8 bits mance automotive audio applications with its large on-chip SRAM, mask programmable ROM, multiple internal buses to SPI 2 eliminate I/O bottlenecks, and an innovative digital applications TWI Yes interface (DAI). SRC Performance 128 dB As shown in the functional block diagram on Page 1, the processor uses two computational units to deliver a significant Shared Memory Support 256-Ball BGA only performance increase over the previous SHARC processors on a Package 256-Ball BGA, 208-Lead LQFP_EP range of DSP algorithms. Fabricated in a state-of-the-art, high speed, CMOS process, the processor achieves an instruction cycle time of up to 2.5 ns at 400 MHz. With its SIMD computa- The diagram on Page 1 shows the two clock domains. The core tional hardware, the processor can perform 2.4 GFLOPS clock domain contains the following features. running at 400 MHz. • Two processing elements (PEx, PEy), each of which com- Table 1 shows performance benchmarks for the ADSP-21369 prises an ALU, multiplier, shifter, and data register file processor. • Data address generators (DAG1, DAG2) • Program sequencer with instruction cache
Table 1. Processor Benchmarks (at 400 MHz)
• PM and DM buses capable of supporting two 64-bit data
Speed
transfers between memory and the core at every core pro-
Benchmark Algorithm (at 400 MHz)
cessor cycle 1024 Point Complex FFT (Radix 4, with Reversal) 23.2 s • One periodic interval timer with pinout FIR Filter (per Tap)1 1.25 ns • On-chip SRAM (2M bit) IIR Filter (per Biquad)1 5.0 ns • JTAG test access port for emulation and boundary scan. Matrix Multiply (Pipelined) The JTAG provides software debug through user break- [3×3] × [3×1] 11.25 ns points which allows flexible exception handling. [4×4] × [4×1] 20.0 ns The block diagram on Page 1 also shows the peripheral clock Divide (y/x) 8.75 ns domain (also known as the I/O processor) and contains the fol- Inverse Square Root 13.5 ns lowing features: 1 Assumes two files in multichannel SIMD mode. • IOD0 (periphera l DMA) and IOD1 (external port DMA) buses for 32-bit data transfers
Table 2. Product Features
• Peripheral and external port buses for core connection • External port with an AMI and SDRAM controller
Feature ADSP-21369
• 4 units for PWM control Frequency 400 MHz • 1 MTM unit for internal-to-internal memory transfers RAM 2M bits • Digital applications interface that includes four precision ROM 6M bits clock generators (PCG), a input data port (IDP) for serial Pulse-Width Modulation Yes and parallel interconnect, an S/PDIF receiver/transmitter, four asynchronous sample rate converters, eight serial S/PDIF Yes ports, a flexible signal routing unit (DAI SRU). SDRAM Memory Bus Width 32 bits/16 bits • Digital peripheral interface that includes three timers, a 2- Serial Ports 8 wire interface, two UARTs, two serial peripheral interfaces (SPI), 2 precision clock generators (PCG) and a flexible sig- IDP Yes nal routing unit (DPI SRU). DAI Yes UART 2 Rev. H | Page 3 of 60 | March 2019 Document Outline Summary Dedicated Audio Components Table of Contents Revision History General Description SHARC Family Core Architecture SIMD Computational Engine Independent, Parallel Computation Units Data Register File Context Switch Universal Registers Timer Single-Cycle Fetch of Instruction and Four Operands Instruction Cache Data Address Generators with Zero-Overhead Hardware Circular Buffer Support Flexible Instruction Set On-Chip Memory On-Chip Memory Bandwidth ROM-Based Security Family Peripheral Architecture External Port SDRAM Controller External Memory Shared External Memory External Port Throughput Asynchronous Memory Controller Pulse-Width Modulation Digital Applications Interface (DAI) Serial Ports S/PDIF-Compatible Digital Audio Receiver/Transmitter Synchronous/Asynchronous Sample Rate Converter Input Data Port Precision Clock Generators Digital Peripheral Interface (DPI) Serial Peripheral (Compatible) Interface UART Port Peripheral Timers 2-Wire Interface Port (TWI) I/O Processor Features DMA Controller Delay Line DMA System Design Program Booting Power Supplies Target Board JTAG Emulator Connector Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Function Descriptions Specifications Operating Conditions Electrical Characteristics ESD Caution Maximum Power Dissipation Absolute Maximum Ratings Timing Specifications Core Clock Requirements Voltage Controlled Oscillator Power-Up Sequencing Clock Input Clock Signals Reset Interrupts Core Timer Timer PWM_OUT Cycle Timing Timer WDTH_CAP Timing Pin to Pin Direct Routing (DAI and DPI) Precision Clock Generator (Direct Pin Routing) Flags SDRAM Interface Timing (166 MHz SDCLK) SDRAM Interface Enable/Disable Timing (166 MHz SDCLK) Memory Read Memory Write Asynchronous Memory Interface (AMI) Enable/Disable Shared Memory Bus Request Serial Ports Input Data Port Parallel Data Acquisition Port (PDAP) Pulse-Width Modulation Generators Sample Rate Converter—Serial Input Port Sample Rate Converter—Serial Output Port S/PDIF Transmitter S/PDIF Transmitter—Serial Input Waveforms S/PDIF Transmitter Input Data Timing Oversampling Clock (TxCLK) Switching Characteristics S/PDIF Receiver Internal Digital PLL Mode SPI Interface—Master SPI Interface—Slave JTAG Test Access Port and Emulation Output Drive Currents Test Conditions Capacitive Loading Thermal Characteristics 256-Ball BGA_ED Pinout 208-Lead LQFP_EP Pinout Package Dimensions Surface-Mount Design Ordering Guide
