Datasheet M29W040B (STMicroelectronics) - 4
| Manufacturer | STMicroelectronics |
| Description | 4 Mbit (512Kb x8, Uniform Block) Low Voltage Single Supply Flash Memory |
| Pages / Page | 20 / 4 — M29W040B. BUS OPERATIONS. Standby. Bus Read. Automatic Standby. Bus … |
| File Format / Size | PDF / 444 Kb |
| Document Language | English |
M29W040B. BUS OPERATIONS. Standby. Bus Read. Automatic Standby. Bus Write. Special Bus Operations. Electronic Signature
Model Line for this Datasheet
- M29W040B120K1 M29W040B120K6 M29W040B120N1 M29W040B120N6 M29W040B120NZ1 M29W040B120NZ6 M29W040B55K1 M29W040B55K6 M29W040B55N1 M29W040B55N6 M29W040B55NZ1 M29W040B55NZ6 M29W040B70K1 M29W040B70K6 M29W040B70N1 M29W040B70N6 M29W040B70NZ1 M29W040B70NZ6 M29W040B90K1 M29W040B90K6 M29W040B90N1 M29W040B90N6 M29W040B90NZ1 M29W040B90NZ6
Text Version of Document
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M29W040B BUS OPERATIONS Standby.
When Chip Enable is High, VIH, the There are five standard bus operations that control memory enters Standby mode and the Data In- the device. These are Bus Read, Bus Write, Out- puts/Outputs pins are placed in the high-imped- put Disable, Standby and Automatic Standby. See ance state. To reduce the Supply Current to the Table 4, Bus Operations, for a summary. Typically Standby Supply Current, ICC2, Chip Enable should glitches of less than 5ns on Chip Enable or Write be held within VCC ± 0.2V. For the Standby current Enable are ignored by the memory and do not af- level see Table 10, DC Characteristics. fect bus operations. During program or erase operations the memory
Bus Read.
Bus Read operations read from the will continue to use the Program/Erase Supply memory cells, or specific registers in the Com- Current, ICC3, for Program or Erase operations un- mand Interface. A valid Bus Read operation in- til the operation completes. volves setting the desired address on the Address
Automatic Standby.
If CMOS levels (VCC ± 0.2V) Inputs, applying a Low signal, VIL, to Chip Enable are used to drive the bus and the bus is inactive for and Output Enable and keeping Write Enable 150ns or more the memory enters Automatic High, VIH. The Data Inputs/Outputs will output the Standby where the internal Supply Current is re- value, see the Figure 8, Read Mode AC Wave- duced to the Standby Supply Current, ICC2. The forms, and Table 11, Read AC Characteristics, for Data Inputs/Outputs will still output data if a Bus details of when the output becomes valid. Read operation is in progress.
Bus Write.
Bus Write operations write to the
Special Bus Operations
Command Interface. A valid Bus Write operation Additional bus operations can be performed to begins by setting the desired address on the Ad- read the Electronic Signature and also to apply dress Inputs. The Address Inputs are latched by and remove Block Protection. These bus opera- the Command Interface on the falling edge of Chip tions are intended for use by programming equip- Enable or Write Enable, whichever occurs last. ment and are not usually used in applications. The Data Inputs/Outputs are latched by the Com- They require VID to be applied to some pins. mand Interface on the rising edge of Chip Enable
Electronic Signature.
The memory has two or Write Enable, whichever occurs first. Output En- codes, the manufacturer code and the device able must remain High, VIH, during the whole Bus code, that can be read to identify the memory. Write operation. See Figures 9 and 10 Write AC These codes can be read by applying the signals Waveforms, and Tables 12 and 13, Write AC listed in Table 4, Bus Operations. Characteristics, for details of the timing require- ments.
Block Protection
and
Blocks Unprotection.
Each block can be separately protected against acci-
Output Disable.
The Data Inputs/Outputs are in dental Program or Erase. Protected blocks can be the high impedance state when Output Enable is unprotected to allow data to be changed. Block High, VIH. Protection and Blocks Unprotection operations must only be performed on programming equip- ment. For further information refer to Application Note AN1122, Applying Protection and Unprotec- tion to M29 Series Flash.
Table 4. Bus Operations Data Operation E G W Address Inputs Inputs/Outputs
Bus Read VIL VIL VIH Cell Address Data Output Bus Write VIL VIH VIL Command Address Data Input Output Disable X VIH VIH X Hi-Z Standby VIH X X X Hi-Z Read Manufacturer A0 = V V IL, A1 = VIL, A9 = VID, 20h Code IL VIL VIH Others VIL or VIH A0 = VIL, A1 = VIL, A9 = VID, Read Device Code VIL VIL VIH E3h Others VIL or VIH Note: X = VIL or VIH. 4/20 Document Outline Table 1. Signal Names Table 2. Absolute Maximum Ratings (1) Table 3. Uniform Block Addresses, M29W040B Table 4. Bus Operations Table 5. Commands Read/Reset. Auto Select. Program, Unlock Bypass Program, Chip Erase, Block Erase. Unlock Bypass. Unlock Bypass Reset. Erase Suspend. Erase Resume. Table 6. Program, Erase Times and Program, Erase Endurance Cycles (TA = 0 to 70˚C or –40 to 85˚C) Table 7. Status Register Bits Table 8. AC Measurement Conditions Table 9. Capacitance (TA = 25 ˚C, f = 1 MHz) Table 10. DC Characteristics (TA = 0 to 70˚C or –40 to 85˚C) Table 11. Read AC Characteristics (TA = 0 to 70˚C or –40 to 85˚C) Table 12. Write AC Characteristics, Write Enable Controlled (TA = 0 to 70˚C or –40 to 85˚C) Table 13. Write AC Characteristics, Chip Enable Controlled (TA = 0 to 70˚C or –40 to 85˚C) Table 14. Ordering Information Scheme Table 15. PLCC32 – 32 lead Plastic Leaded Chip Carrier, Package Mechanical Data Table 16. TSOP32 – 32 lead Plastic Thin Small Outline, 8 x 20mm, Package Mechanical Data Table 17. TSOP32 – 32 lead Plastic Thin Small Outline, 8 x 14mm, Package Mechanical Data Table 18. Revision History SUMMARY DESCRIPTION SIGNAL DESCRIPTIONS Address Inputs (A0-A18). Data Inputs/Outputs (DQ0-DQ7). Chip Enable (E). Output Enable (G). Write Enable (W). VCC Supply Voltage. VSS Ground. BUS OPERATIONS Bus Read. Bus Write. Output Disable. Standby. Automatic Standby. Special Bus Operations Electronic Signature. Block Protection and Blocks Unprotection. COMMAND INTERFACE Read/Reset Command. Auto Select Command. Program Command. Unlock Bypass Command. Unlock Bypass Program Command. Unlock Bypass Reset Command. Chip Erase Command. Block Erase Command. Erase Suspend Command. Erase Resume Command. STATUS REGISTER Data Polling Bit (DQ7). Toggle Bit (DQ6). Error Bit (DQ5). Erase Timer Bit (DQ3). Alternative Toggle Bit (DQ2). Figure 1. Logic Diagram Figure 2. PLCC Connections Figure 3. TSOP Connections Figure 4. Data Polling Flowchart Figure 5. Data Toggle Flowchart Figure 6. AC Testing Input Output Waveform Figure 7. AC Testing Load Circuit Figure 8. Read Mode AC Waveforms Figure 9. Write AC Waveforms, Write Enable Controlled Figure 10. Write AC Waveforms, Chip Enable Controlled Figure 11. PLCC32 – 32 lead Plastic Leaded Chip Carrier, Package Outline Figure 12. TSOP32 – 32 lead Plastic Thin Small Outline, 8 x 20mm, Package Outline Figure 13. TSOP32 – 32 lead Plastic Thin Small Outline, 8 x 14mm, Package Outline
M29W040B BUS OPERATIONS Standby.
When Chip Enable is High, VIH, the There are five standard bus operations that control memory enters Standby mode and the Data In- the device. These are Bus Read, Bus Write, Out- puts/Outputs pins are placed in the high-imped- put Disable, Standby and Automatic Standby. See ance state. To reduce the Supply Current to the Table 4, Bus Operations, for a summary. Typically Standby Supply Current, ICC2, Chip Enable should glitches of less than 5ns on Chip Enable or Write be held within VCC ± 0.2V. For the Standby current Enable are ignored by the memory and do not af- level see Table 10, DC Characteristics. fect bus operations. During program or erase operations the memory
Bus Read.
Bus Read operations read from the will continue to use the Program/Erase Supply memory cells, or specific registers in the Com- Current, ICC3, for Program or Erase operations un- mand Interface. A valid Bus Read operation in- til the operation completes. volves setting the desired address on the Address
Automatic Standby.
If CMOS levels (VCC ± 0.2V) Inputs, applying a Low signal, VIL, to Chip Enable are used to drive the bus and the bus is inactive for and Output Enable and keeping Write Enable 150ns or more the memory enters Automatic High, VIH. The Data Inputs/Outputs will output the Standby where the internal Supply Current is re- value, see the Figure 8, Read Mode AC Wave- duced to the Standby Supply Current, ICC2. The forms, and Table 11, Read AC Characteristics, for Data Inputs/Outputs will still output data if a Bus details of when the output becomes valid. Read operation is in progress.
Bus Write.
Bus Write operations write to the
Special Bus Operations
Command Interface. A valid Bus Write operation Additional bus operations can be performed to begins by setting the desired address on the Ad- read the Electronic Signature and also to apply dress Inputs. The Address Inputs are latched by and remove Block Protection. These bus opera- the Command Interface on the falling edge of Chip tions are intended for use by programming equip- Enable or Write Enable, whichever occurs last. ment and are not usually used in applications. The Data Inputs/Outputs are latched by the Com- They require VID to be applied to some pins. mand Interface on the rising edge of Chip Enable
Electronic Signature.
The memory has two or Write Enable, whichever occurs first. Output En- codes, the manufacturer code and the device able must remain High, VIH, during the whole Bus code, that can be read to identify the memory. Write operation. See Figures 9 and 10 Write AC These codes can be read by applying the signals Waveforms, and Tables 12 and 13, Write AC listed in Table 4, Bus Operations. Characteristics, for details of the timing require- ments.
Block Protection
and
Blocks Unprotection.
Each block can be separately protected against acci-
Output Disable.
The Data Inputs/Outputs are in dental Program or Erase. Protected blocks can be the high impedance state when Output Enable is unprotected to allow data to be changed. Block High, VIH. Protection and Blocks Unprotection operations must only be performed on programming equip- ment. For further information refer to Application Note AN1122, Applying Protection and Unprotec- tion to M29 Series Flash.
Table 4. Bus Operations Data Operation E G W Address Inputs Inputs/Outputs
Bus Read VIL VIL VIH Cell Address Data Output Bus Write VIL VIH VIL Command Address Data Input Output Disable X VIH VIH X Hi-Z Standby VIH X X X Hi-Z Read Manufacturer A0 = V V IL, A1 = VIL, A9 = VID, 20h Code IL VIL VIH Others VIL or VIH A0 = VIL, A1 = VIL, A9 = VID, Read Device Code VIL VIL VIH E3h Others VIL or VIH Note: X = VIL or VIH. 4/20 Document Outline Table 1. Signal Names Table 2. Absolute Maximum Ratings (1) Table 3. Uniform Block Addresses, M29W040B Table 4. Bus Operations Table 5. Commands Read/Reset. Auto Select. Program, Unlock Bypass Program, Chip Erase, Block Erase. Unlock Bypass. Unlock Bypass Reset. Erase Suspend. Erase Resume. Table 6. Program, Erase Times and Program, Erase Endurance Cycles (TA = 0 to 70˚C or –40 to 85˚C) Table 7. Status Register Bits Table 8. AC Measurement Conditions Table 9. Capacitance (TA = 25 ˚C, f = 1 MHz) Table 10. DC Characteristics (TA = 0 to 70˚C or –40 to 85˚C) Table 11. Read AC Characteristics (TA = 0 to 70˚C or –40 to 85˚C) Table 12. Write AC Characteristics, Write Enable Controlled (TA = 0 to 70˚C or –40 to 85˚C) Table 13. Write AC Characteristics, Chip Enable Controlled (TA = 0 to 70˚C or –40 to 85˚C) Table 14. Ordering Information Scheme Table 15. PLCC32 – 32 lead Plastic Leaded Chip Carrier, Package Mechanical Data Table 16. TSOP32 – 32 lead Plastic Thin Small Outline, 8 x 20mm, Package Mechanical Data Table 17. TSOP32 – 32 lead Plastic Thin Small Outline, 8 x 14mm, Package Mechanical Data Table 18. Revision History SUMMARY DESCRIPTION SIGNAL DESCRIPTIONS Address Inputs (A0-A18). Data Inputs/Outputs (DQ0-DQ7). Chip Enable (E). Output Enable (G). Write Enable (W). VCC Supply Voltage. VSS Ground. BUS OPERATIONS Bus Read. Bus Write. Output Disable. Standby. Automatic Standby. Special Bus Operations Electronic Signature. Block Protection and Blocks Unprotection. COMMAND INTERFACE Read/Reset Command. Auto Select Command. Program Command. Unlock Bypass Command. Unlock Bypass Program Command. Unlock Bypass Reset Command. Chip Erase Command. Block Erase Command. Erase Suspend Command. Erase Resume Command. STATUS REGISTER Data Polling Bit (DQ7). Toggle Bit (DQ6). Error Bit (DQ5). Erase Timer Bit (DQ3). Alternative Toggle Bit (DQ2). Figure 1. Logic Diagram Figure 2. PLCC Connections Figure 3. TSOP Connections Figure 4. Data Polling Flowchart Figure 5. Data Toggle Flowchart Figure 6. AC Testing Input Output Waveform Figure 7. AC Testing Load Circuit Figure 8. Read Mode AC Waveforms Figure 9. Write AC Waveforms, Write Enable Controlled Figure 10. Write AC Waveforms, Chip Enable Controlled Figure 11. PLCC32 – 32 lead Plastic Leaded Chip Carrier, Package Outline Figure 12. TSOP32 – 32 lead Plastic Thin Small Outline, 8 x 20mm, Package Outline Figure 13. TSOP32 – 32 lead Plastic Thin Small Outline, 8 x 14mm, Package Outline
