Datasheet MLX75026 (Melexis)

ManufacturerMelexis
DescriptionQVGA Time-of-Flight Sensor
Pages / Page64 / 1 — MLX75026 QVGA Time-of-Flight Sensor. Features & Benefits. Description
File Format / SizePDF / 3.1 Mb
Document LanguageEnglish

MLX75026 QVGA Time-of-Flight Sensor. Features & Benefits. Description

Datasheet MLX75026 Melexis

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MLX75026 QVGA Time-of-Flight Sensor
PRELIMINARY DATASHEET v0.5
Features & Benefits Description
 1/4" optical Time-of-Flight image sensor MLX75026 is a fully integrated optical Time-of-  QVGA (320 x 240) pixel array Flight image sensor. It’s perfectly suited for  10 x 10 µm DepthSense pixels automotive and non-automotive applications,  Integrated microlenses including, but not limited to, gesture  Backside illumination (BSI technology) recognition, driver monitoring, skeleton  External quantum efficiency 51% (850nm) tracking, people or obstacle detection and  External quantum efficiency 28% (940nm) traffic monitoring. The sensor features a QVGA  High distance accuracy due to programmable (320x240) pixel array based on the modulating frequencies up to 100MHz DepthSense pixel technology. Combined  AC Demodulation contrast 85% (40 MHz) with a modulated light source this sensor is  AC Demodulation contrast 78 % (100 MHz) capable of measuring object distance and  Differential light source control with phase reflectivity under extreme background light delay feedback loop conditions, 120KLUX robust when using lens  Full resolution distance framerate of with filter. This distance information can be max. 180 FPS (4 phases, Tint <250µs, used to calculate a complete 3D point cloud 4lane@960mbps MIPI configuration) representation of a scene. Full resolution  Up to 8 raw phases (or quads) per frame image acquisition up to 180 distance frames  Per-phase statistics & diagnostics per second while supplied to a microcontroller  Continuous or triggered operation mode(s) via a standardized MIPI CSI-2 serial camera  Configurable over I2C (up to 400kHz) interface. The device is available in a cost  CSI-2 serial data output, MIPI D-PHY, 1 clock optimized encapsulated package and offers a lane, 2 or 4 data lanes (<960 Mbps/lane) variety of integration possibilities.  Build-in temperature sensor  Region of interest (ROI) selection  Integrated support for binning (2x2, 4x4, 8x8)  Horizontal mirror & vertical flip image modes  9.2 x 7.8 x 1.0 mm encapsulated BGA package  Number of pins = 80  Ambient operating temperature range of -40 +105°C  MSL level 3 rated  AEC-Q100 qualified (grade 2) Preliminary Datasheet: Melexis reserves the right to change the product and specifications without prior notice. The information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the device. Melexis cannot assume responsibility for any problems arising out of the use of these circuits. Document Outline Table of Contents Document Revision History Ordering Information 1. System Architecture 2. Sensor Block Diagram 3. Electrical Specifications 3.1. Absolute Maximum Ratings 3.2. Typical Operating Conditions 3.3. Video Interface 3.3.1. MIPI DC specification 3.3.2. MIPI AC specification 3.4. Power Consumption 3.5. Maximum Distance Frame Rate 3.6. Decoupling Recommendations 3.7. Power-up Sequence 3.8. Input Clock Requirements 3.9. I2C Specifications 4. Optical Characteristics 4.1. QVGA Pixel Array Configuration 4.2. Pixel & Image Array Characteristics 4.3. CRA (Chief Ray Angle) 4.4. MTF (Modulation Transfer Function) 4.5. Application Lens Design Recommendations 5. Communication Interface(s) 5.1. I2C (Inter-Integrated Circuit) 5.1.1. I2C Timing Sequence 5.1.2. Single I2C Read 5.1.3. Sequential I2C Read 5.1.4. Single I2C Write 5.1.5. Sequential I2C Write 5.1.6. I2C Slave Address 5.2. MIPI Alliance CSI-2 Description 5.2.1. Packet Structure 5.2.2. Data Format RAW12 5.2.2.1. Data Format in 4 Lane MIPI Configuration 5.2.2.2. Data Format in 2 Lane MIPI Configuration 6. Start-up Sequence 6.1. Initialization Process 6.2. Initialization Register Map 7. Register Settings 7.1. Video Output Configuration 7.2. Modes of Operation 7.3. Data Output Modes 7.4. HMAX & Frame Read-Out Time 7.4.1. PLLSSETUP 7.4.2. PRETIME 7.4.3. RANDNM0 7.5. PARAM_HOLD 7.6. USER_ID Register 7.7. Modulation Frequency 7.8. Frame Structure & Frame Rate 7.9. FRAME_STARTUP 7.10. FRAME_TIME 7.11. PHASE_COUNT 7.12. Px_PREHEAT, Px_PREMIX 7.13. Px_INTEGRATION 7.14. Px_PHASE_SHIFT 7.15. Px_PHASE_IDLE (or V-blanking) 7.16. Px_LEDEN 7.17. Px_DMIX0, Px_DMIX1 & Px_STATIC_LED 7.18. Analog Delay Setting 7.18.1. Coarse Delay 7.18.2. Fine Delay 7.18.3. Super Fine 7.19. Pixel Binning 7.20. Region of Interest (ROI) 7.21. Flip & Mirror 7.22. Temperature Sensor 7.23. Pixel & Phase Statistics 7.24. PN9 Test Pattern 7.25. Duty Cycle Adjustment 7.26. Illumination Signal (subLVDS or CMOS) 8. MetaData Description 8.1. Embedded Data Format in 4 Lane MIPI Configuration 8.2. Embedded Data Format in 2 Lane MIPI Configuration 9. Distance & Amplitude Calculation 10. Package Outline 10.1. Pinout & Equivalent I/O Circuitry 10.2. Mechanical Dimensions 10.3. PCB Landing Pattern & Layout Recommendations 10.4. Package Marking 10.5. Cover Tape Removal Disclaimer
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