Datasheet ADP1821 (Analog Devices) - 9
| Manufacturer | Analog Devices |
| Description | Step-Down DC-to-DC Controller |
| Pages / Page | 24 / 9 — ADP1821. THEORY OF OPERATION. CURRENT-LIMIT SCHEME. SOFT START. ERROR … |
| Revision | C |
| File Format / Size | PDF / 828 Kb |
| Document Language | English |
ADP1821. THEORY OF OPERATION. CURRENT-LIMIT SCHEME. SOFT START. ERROR AMPLIFIER
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ADP1821 THEORY OF OPERATION
The ADP1821 is a versatile, economical, synchronous-rectified, control loop. A detailed design procedure for compensating the fixed-frequency, PWM, voltage mode step-down controller system is provided in the Compensating the Voltage Mode Buck capable of generating an output voltage as low as 0.6 V. It is ideal Regulator section. for a wide range of high power applications, such as DSP power The error amplifier output is clamped between a lower limit of and processor core power in telecommunications, medical about 0.7 V and a higher limit of about 2.4 V. When the COMP pin imaging, and industrial applications. The ADP1821 controller is low, the switching duty cycle goes to 0%, and when the COMP operates from a 3.7 V to 5.5 V supply with a power input voltage pin is high, the switching duty cycle goes to the maximum. ranging from 1.0 V to 24 V. The SS pin is an auxiliary positive input to the error amplifier. The ADP1821 operates at a fixed, internally set 300 kHz or Whichever voltage is lowest, SS or the internal 0.6 V reference, 600 kHz switching frequency that is controlled by the state of controls the FB pin voltage and thus the output. As a conse- the FREQ input. The high frequency reduces external compo- quence, if two of these inputs are close to each other, a small nent size and cost while maintaining high efficiency. For noise offset is imposed on the error amplifier. sensitive applications where the switching frequency needs to be more tightly controlled, synchronize the ADP1821 to an external
CURRENT-LIMIT SCHEME
signal whose frequency is between 300 kHz and 1.2 MHz. The ADP1821 employs a unique, programmable, cycle-by-cycle, The ADP1821 includes adjustable soft start with output reverse- lossless current-limit circuit that uses an ordinary, inexpensive current protection, and a unique adjustable, lossless current resistor to set the threshold. Every switching cycle, the synchronous limit. It operates over the −40°C to +125°C temperature range rectifier turns on for a minimum time and the voltage drop across and is available in a space-saving, 16-lead QSOP. the MOSFET RDSON is measured to determine if the current is too high.
SOFT START
This measurement is done by an internal current limit com- When powering up or resuming operation after shutdown, over- parator and an external current-limit set resistor. The resistor load, or short-circuit conditions, the ADP1821 employs an is connected between the switch node (that is the drain of the adjustable soft start feature that reduces input current transients rectifier MOSFET) and the CSL pin. The CSL pin, which is the and prevents output voltage overshoot at start-up and overload inverting input of the comparator, forces 50 μA through the conditions. The soft start period is set by the value of the soft resistor to create an offset voltage drop across it. start capacitor, CSS, between SS and GND. When the inductor current is flowing in the MOSFET rectifier, When starting the ADP1821, CSS is initially discharged. It is its drain is forced below PGND by the voltage drop across its enabled when SHDN is high and VCC is above the undervoltage RDSON. If the RDSON voltage drop exceeds the preset drop on the lockout threshold. CSS begins charging to 0.8 V through an current-limit set resistor, the inverting comparator input is internal 100 kΩ resistor. As CSS charges, the regulation voltage at similarly forced below PGND and an overcurrent fault is flagged. FB is limited to the lesser of either the voltage at SS or the internal The normal transient ringing on the switch node is ignored 0.6 V reference voltage. As the voltage at SS rises, the output for 100 ns after the synchronous rectifier turns on, therefore, voltage rises proportionally until the voltage at SS exceeds 0.6 V. At the over current condition must also persist for 100 ns for a this time, the output voltage is regulated to the desired voltage. fault to be flagged. If the output voltage is precharged prior to turn-on, the ADP1821 When the ADP1821 senses an overcurrent condition, the next limits reverse inductor current, which would discharge the output switching cycle is suppressed, the soft start capacitor is discharged voltage. Once the voltage at SS exceeds the 0.6 V regulation voltage, through an internal 2.5 kΩ resistor, and the error amplifier the reverse current is re-enabled to allow the output voltage output voltage is pulled down. The output behaves like a regulation to be independent of load current. constant current source around the preset current limit when
ERROR AMPLIFIER
the overcurrent condition exists. The ADP1821 remains in this The ADP1821 error amplifier is an operational amplifier. The mode for as long as the overcurrent condition persists. In the ADP1821 senses the output voltages through an external event of a short circuit, the short-circuit output current is the resistor divider at the FB pin. The FB pin is the inverting input current limit set by the RCL resistor and is monitored cycle by to the error amplifier. The error amplifier compares this feed- cycle. When the overcurrent condition is removed, operation back voltage to the internal 0.6 V reference, and the output of resumes in soft start mode. the error amplifier appears at the COMP pin. The COMP pin The ADP1821 also offers a technique for implementing a voltage then directly controls the duty cycle of the switching current-limit foldback in the event of a short circuit with the converter. use of an additional resistor. See the Setting the Current Limit A series/parallel RC network is tied between the FB pin and the section for more information. COMP pin to provide the compensation for the buck converter Rev. C | Page 9 of 24 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION SIMPLIFIED BLOCK DIAGRAM PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION SOFT START ERROR AMPLIFIER CURRENT-LIMIT SCHEME MOSFET DRIVERS INPUT VOLTAGE RANGE SETTING THE OUTPUT VOLTAGE SWITCHING FREQUENCY CONTROL AND SYNCHRONIZATION COMPENSATION POWER-GOOD INDICATOR THERMAL SHUTDOWN SHUTDOWN CONTROL APPLICATION INFORMATION SELECTING THE INPUT CAPACITOR OUTPUT LC FILTER SELECTING THE MOSFETS SETTING THE CURRENT LIMIT FEEDBACK VOLTAGE DIVIDER COMPENSATING THE VOLTAGE MODE BUCK REGULATOR Type II Compensator Type III Compensator SETTING THE SOFT START PERIOD PCB LAYOUT GUIDELINE RECOMMENDED COMPONENT MANUFACTURERS APPLICATION CIRCUITS OUTLINE DIMENSIONS ORDERING GUIDE
ADP1821 THEORY OF OPERATION
The ADP1821 is a versatile, economical, synchronous-rectified, control loop. A detailed design procedure for compensating the fixed-frequency, PWM, voltage mode step-down controller system is provided in the Compensating the Voltage Mode Buck capable of generating an output voltage as low as 0.6 V. It is ideal Regulator section. for a wide range of high power applications, such as DSP power The error amplifier output is clamped between a lower limit of and processor core power in telecommunications, medical about 0.7 V and a higher limit of about 2.4 V. When the COMP pin imaging, and industrial applications. The ADP1821 controller is low, the switching duty cycle goes to 0%, and when the COMP operates from a 3.7 V to 5.5 V supply with a power input voltage pin is high, the switching duty cycle goes to the maximum. ranging from 1.0 V to 24 V. The SS pin is an auxiliary positive input to the error amplifier. The ADP1821 operates at a fixed, internally set 300 kHz or Whichever voltage is lowest, SS or the internal 0.6 V reference, 600 kHz switching frequency that is controlled by the state of controls the FB pin voltage and thus the output. As a conse- the FREQ input. The high frequency reduces external compo- quence, if two of these inputs are close to each other, a small nent size and cost while maintaining high efficiency. For noise offset is imposed on the error amplifier. sensitive applications where the switching frequency needs to be more tightly controlled, synchronize the ADP1821 to an external
CURRENT-LIMIT SCHEME
signal whose frequency is between 300 kHz and 1.2 MHz. The ADP1821 employs a unique, programmable, cycle-by-cycle, The ADP1821 includes adjustable soft start with output reverse- lossless current-limit circuit that uses an ordinary, inexpensive current protection, and a unique adjustable, lossless current resistor to set the threshold. Every switching cycle, the synchronous limit. It operates over the −40°C to +125°C temperature range rectifier turns on for a minimum time and the voltage drop across and is available in a space-saving, 16-lead QSOP. the MOSFET RDSON is measured to determine if the current is too high.
SOFT START
This measurement is done by an internal current limit com- When powering up or resuming operation after shutdown, over- parator and an external current-limit set resistor. The resistor load, or short-circuit conditions, the ADP1821 employs an is connected between the switch node (that is the drain of the adjustable soft start feature that reduces input current transients rectifier MOSFET) and the CSL pin. The CSL pin, which is the and prevents output voltage overshoot at start-up and overload inverting input of the comparator, forces 50 μA through the conditions. The soft start period is set by the value of the soft resistor to create an offset voltage drop across it. start capacitor, CSS, between SS and GND. When the inductor current is flowing in the MOSFET rectifier, When starting the ADP1821, CSS is initially discharged. It is its drain is forced below PGND by the voltage drop across its enabled when SHDN is high and VCC is above the undervoltage RDSON. If the RDSON voltage drop exceeds the preset drop on the lockout threshold. CSS begins charging to 0.8 V through an current-limit set resistor, the inverting comparator input is internal 100 kΩ resistor. As CSS charges, the regulation voltage at similarly forced below PGND and an overcurrent fault is flagged. FB is limited to the lesser of either the voltage at SS or the internal The normal transient ringing on the switch node is ignored 0.6 V reference voltage. As the voltage at SS rises, the output for 100 ns after the synchronous rectifier turns on, therefore, voltage rises proportionally until the voltage at SS exceeds 0.6 V. At the over current condition must also persist for 100 ns for a this time, the output voltage is regulated to the desired voltage. fault to be flagged. If the output voltage is precharged prior to turn-on, the ADP1821 When the ADP1821 senses an overcurrent condition, the next limits reverse inductor current, which would discharge the output switching cycle is suppressed, the soft start capacitor is discharged voltage. Once the voltage at SS exceeds the 0.6 V regulation voltage, through an internal 2.5 kΩ resistor, and the error amplifier the reverse current is re-enabled to allow the output voltage output voltage is pulled down. The output behaves like a regulation to be independent of load current. constant current source around the preset current limit when
ERROR AMPLIFIER
the overcurrent condition exists. The ADP1821 remains in this The ADP1821 error amplifier is an operational amplifier. The mode for as long as the overcurrent condition persists. In the ADP1821 senses the output voltages through an external event of a short circuit, the short-circuit output current is the resistor divider at the FB pin. The FB pin is the inverting input current limit set by the RCL resistor and is monitored cycle by to the error amplifier. The error amplifier compares this feed- cycle. When the overcurrent condition is removed, operation back voltage to the internal 0.6 V reference, and the output of resumes in soft start mode. the error amplifier appears at the COMP pin. The COMP pin The ADP1821 also offers a technique for implementing a voltage then directly controls the duty cycle of the switching current-limit foldback in the event of a short circuit with the converter. use of an additional resistor. See the Setting the Current Limit A series/parallel RC network is tied between the FB pin and the section for more information. COMP pin to provide the compensation for the buck converter Rev. C | Page 9 of 24 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION SIMPLIFIED BLOCK DIAGRAM PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION SOFT START ERROR AMPLIFIER CURRENT-LIMIT SCHEME MOSFET DRIVERS INPUT VOLTAGE RANGE SETTING THE OUTPUT VOLTAGE SWITCHING FREQUENCY CONTROL AND SYNCHRONIZATION COMPENSATION POWER-GOOD INDICATOR THERMAL SHUTDOWN SHUTDOWN CONTROL APPLICATION INFORMATION SELECTING THE INPUT CAPACITOR OUTPUT LC FILTER SELECTING THE MOSFETS SETTING THE CURRENT LIMIT FEEDBACK VOLTAGE DIVIDER COMPENSATING THE VOLTAGE MODE BUCK REGULATOR Type II Compensator Type III Compensator SETTING THE SOFT START PERIOD PCB LAYOUT GUIDELINE RECOMMENDED COMPONENT MANUFACTURERS APPLICATION CIRCUITS OUTLINE DIMENSIONS ORDERING GUIDE
