Datasheet SLG47004 (Dialog Semiconductor) - 11
| Manufacturer | Dialog Semiconductor |
| Description | GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features |
| Pages / Page | 243 / 11 — SLG47004. Preliminary. Pinout. 2.1 PIN CONFIGURATION - STQFN-24L. Pin # … |
| File Format / Size | PDF / 5.6 Mb |
| Document Language | English |
SLG47004. Preliminary. Pinout. 2.1 PIN CONFIGURATION - STQFN-24L. Pin # Signal Name Pin Functions. (Top View). STQFN-24. ACMPx+. ACMPx-
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SLG47004
GreenPAK Programmable Mixed-Signal Matrix
Preliminary
with In-System Programmability and Advanced Analog Features
2 Pinout 2.1 PIN CONFIGURATION - STQFN-24L Pin # Signal Name Pin Functions
1 VDDA Analog Power Supply T 2 AGND Analog Ground U 3 OA0- Op Amp0 Inverting Input _O 1- 1+ 1 A A A 6 5 4 OA0+ Op Amp0 Non-Inverting Input O O O I0 IO IO 5 OA0_OUT Op Amp0_OUT/ACMP0L+ / 24 6 RH0_A Digital Rheostat 0 Terminal A V 23 22 21 20 19 DDA 1 18 IO4 7 RH0_B Digital Rheostat 0 Terminal B AGND 2 17 IO3 8 RH1_A Digital Rheostat 1 Terminal A 9 RH1_B Digital Rheostat 1 Terminal B OA0- 3 16 IO2 10 SCL I2C_SCL OA0+ 4 15 IO1 11 SDA I2C_SDA 14 GPIO, ACMP0L-, ACMP1L-, EXT_OSC0_IN, OA0_OUT 5 GND 12 IO0 Vref0_Out or Temp_Sens_Out RH0_A 6 13 VDD 8 9 10 7 11 12 13 VDD Digital Power Supply 14 GND Digital Ground B L 0 _B _A A 0 1 1_ C D IO 15 IO1 GPIO, Chop_ACMP+, Vref1_OUT or S S Temp_Sens_Out, EXT_OSC1_IN or SLA_0 H H H R R R 16 IO2 GPIO, ACMP0L+, EXT_OSC2_IN, SLA_1
(Top View)
17 IO3 GPIO, AS_1_A, ACMP1L+ or SLA_2
STQFN-24
18 IO4 GPIO, AS_1_B, Chop_ACMP-or SLA_3 19 IO5 GPIO, AS_0_B 20 IO6 GPIO, AS_0_A, HD_Buff_Out, In Amp_Vref 21 I0 GPI, In Amp_OUT 22 OA1_OUT Op Amp1_OUT, ACMP1L+ 23 OA1+ Op Amp1 Non-inverting Input 24 OA1- Op Amp1 Inverting Input Legend:
ACMPx+
: ACMPx Positive Input
ACMPx-
: ACMPx Negative Input
SCL
: I2C Clock Input
SDA
: I2C Data Input/Output
Vrefx
: Voltage Reference Output
SLA:
Slave Address
Table 1: Functional Pin Description Pin No. Pin Signal Input Output Function Name Name Options Options STQFN 24L
1 VDDA VDDA Analog Power Supply -- -- 2 AGND AGND Analog Ground -- -- 3 OA0- OA0- Op Amp0 Inverting Input Analog -- 4 OA0+ OA0+ Op Amp0 Non-Inverting Input Analog -- OA0_OUT Op Amp0 Output -- Analog OA0_OUT 5 ACMP0L+ Analog Comparator 0 Positive In- put Analog -- 6 RH0_A RH0_A Digital Rheostat 0 Terminal A -- --
Datasheet Revision 2.1 13-Nov-2020
CFR0011-120-00 11 of 243 © 2020 Dialog Semiconductor Document Outline General Description Key Features Applications 1 Block Diagram 2 Pinout 2.1 Pin Configuration - STQFN-24L 3 Characteristics 3.1 Absolute Maximum Ratings 3.2 Electrostatic Discharge Ratings 3.3 Recommended Operating Conditions 3.4 Electrical Characteristics 3.5 Timing Characteristics 3.6 Oscillator Characteristics 3.6.1 OSC Power-On Delay 3.7 ACMP Characteristics 3.8 Internal Vref Characteristics 3.9 Output Buffers Characteristics 3.10 Analog Temperature Sensor Characteristics 3.11 Programmable Operational Amplifier Characteristics 3.12 100K Digital Rheostat Characteristics 3.13 Analog Switches Characteristics 4 User Programmability 5 IO Pins 5.1 GPIO Pins 5.2 GPI Pins 5.3 Pull-Up/Down Resistors 5.4 Fast Pull-Up/Down during Power-Up 5.5 I2C Mode IO Structure 5.5.1 I2C Mode Structure (for SCL and SDA) 5.6 Matrix OE IO Structure 5.7 GPI Structure 5.7.1 GPI Structure (for I0) 5.8 IO Pins Typical Performance 6 Connection Matrix 6.1 Matrix Input Table 6.2 Matrix Output Table 6.3 Connection Matrix Virtual Inputs 6.4 Connection Matrix Virtual Outputs 7 Combination Function Macrocells 7.1 2-Bit LUT or D Flip-Flop Macrocells 7.1.1 2-Bit LUT or D Flip-Flop Macrocell Used as 2-Bit LUT 7.1.2 Initial Polarity Operations 7.2 2-bit LUT or Programmable Pattern Generator 7.2.1 2-Bit LUT or PGen Macrocell Used as 2-Bit LUT 7.3 3-Bit LUT or D Flip-Flop with Set/Reset Macrocells 7.3.1 3-Bit LUT or D Flip-Flop Macrocells Used as 3-Bit LUTs 7.3.2 Initial Polarity Operations 7.4 4-Bit LUT or D Flip-Flop with Set/Reset Macrocell 7.4.1 4-Bit LUT Macrocell Used as 4-Bit LUT 7.5 3-Bit LUT or Pipe Delay/Ripple Counter Macrocell 7.5.1 3-Bit LUT or Pipe Delay Macrocells Used as 3-Bit LUT 8 Multi-Function Macrocells 8.1 3-Bit LUT or DFF/Latch with 8-Bit Counter/Delay Macrocells 8.1.1 3-Bit LUT or 8-Bit CNT/DLY Block Diagrams 8.1.2 3-Bit LUT or CNT/DLYs Used as 3-Bit LUTs 8.2 4-Bit LUT or DFF/Latch with 16-Bit Counter/Delay Macrocell 8.2.1 4-Bit LUT or DFF/LATCH with 16-Bit CNT/DLY Block Diagram 8.2.2 4-Bit LUT or 16-Bit Counter/Delay Macrocells Used as 4-Bit LUTs 8.3 CNT/DLY/FSM Timing Diagrams 8.3.1 Delay Mode CNT/DLY0 to CNT/DLY6 8.3.2 Count Mode (Count Data: 3), Counter Reset (Rising Edge Detect) CNT/DLY0 to CNT/DLY6 8.3.3 One-Shot Mode CNT/DLY0 to CNT/DLY6 8.3.4 Frequency Detection Mode CNT/DLY0 to CNT/DLY6 8.3.5 Edge Detection Mode CNT/DLY1 to CNT/DLY6 8.3.6 Delayed Edge Detection Mode CNT/DLY0 to CNT/DLY6 8.3.7 CNT/FSM Mode CNT/DLY0 8.3.8 Difference in Counter Value for Counter, Delay, One-Shot, and Frequency Detect Modes 8.4 Wake and Sleep Controller 9 Analog Comparators 9.1 Analog Comparators Overview 9.1.1 ACMP0L Block Diagram 9.1.2 ACMP1L Block Diagram 9.2 Chopper Analog Comparator 9.3 ACMP Sampling Mode 9.4 ACMP Typical Performance 10 Programmable Operational Amplifiers 10.1 General Description 10.2 Modes of Operation 10.2.1 Operational Amplifier Mode 10.2.2 Instrumentation Amplifier Mode 10.2.3 Analog Comparator Mode 10.2.4 Voltage Regulator Mode 10.2.5 Current Sink Mode 10.3 Op Amp Typical Performance 11 Analog Switch Macrocell 11.1 Analog Switch General Description 11.2 Half Bridge Mode 12 Digital Rheostats and Programmable Trim Block 12.1 Potentiometer Mode 12.2 Calculating Actual Resistance 12.3 Digital Rheostat Value Self-programming into the NVM 12.4 Trimming process Using Programmable Trim Block 12.4.1 Trimming Process with Auto-Trim Option Enabled 12.4.2 I2C Controlled Trimming Process with Auto-Trim Option Enabled 12.4.3 Changing Rheostat Value Directly via I2C 12.5 Using Chopper ACMP 13 Programmable Delay/Edge Detector 13.1 Programmable Delay Timing Diagram - Edge Detector Output 14 Additional Logic Function. Deglitch Filter 15 Voltage Reference 15.1 Voltage Reference Overview 15.2 Vref Selection Table 15.3 Vref Block Diagram 16 Clocking 16.1 OSC General Description 16.2 Oscillator0 (2.048 kHz) 16.3 Oscillator1 (2.048 MHz) 16.4 Oscillator2 (25 MHz) 16.5 CNT/DLY Clock Scheme 16.6 External Clocking 16.6.1 IO1 Source for Oscillator0 (2.048 kHz) 16.6.2 IO3 Source for Oscillator1 (2.048 MHz) 16.6.3 IO2 Source for Oscillator2 (25 MHz) 16.7 Oscillators Power-On Delay 16.8 Oscillators Accuracy 17 Power-On Reset 17.1 General Operation 17.2 POR Sequence 17.3 Macrocells Output States During POR Sequence 17.3.1 Initialization 17.3.2 Power-Down 18 I2C Serial Communications Macrocell 18.1 I2C Serial Communications Macrocell Overview 18.2 I2C Serial Communications Device Addressing 18.3 I2C Serial General Timing 18.4 I2C Serial Communications Commands 18.4.1 Byte Write Command 18.4.2 Sequential Write Command 18.4.3 Current Address Read Command 18.4.4 Random Read Command 18.4.5 Sequential Read Command 18.4.6 I2C Serial Reset Command 18.5 Chip Configuration Data Protection 18.6 I2C Serial Command Register Map 18.7 I2C Additional Options 18.7.1 Reading Counter Data via I2C 18.7.2 I2C Byte Write Bit Masking 19 Non-Volatile Memory 19.1 Serial NVM Write Operations 19.2 Serial NVM Read Operations 19.3 Serial NVM Erase Operations 19.4 Acknowledge Polling 19.5 Low power standby mode 19.6 Emulated EEPROM Write Protection 20 Analog Temperature Sensor 21 Register Definitions 21.1 Register Map 22 Package Top Marking System Definition 22.1 STQFN-24L 3 mm x 3 mm x 0.55 mm, 0.4P FCD Package 23 Package Information 23.1 Package outlines FOR STQFN 24L 3 mm x 3 mm x 0.55 mm 0.4P Green Package 23.2 STQFN Handling 23.3 Soldering Information 24 Ordering Information 24.1 Tape and Reel Specifications 25 Layout Guidelines 25.1 STQFN 24L 3 mm x 3 mm x 0.55 mm 0.4P Green Package Glossary Revision History
GreenPAK Programmable Mixed-Signal Matrix
Preliminary
with In-System Programmability and Advanced Analog Features
2 Pinout 2.1 PIN CONFIGURATION - STQFN-24L Pin # Signal Name Pin Functions
1 VDDA Analog Power Supply T 2 AGND Analog Ground U 3 OA0- Op Amp0 Inverting Input _O 1- 1+ 1 A A A 6 5 4 OA0+ Op Amp0 Non-Inverting Input O O O I0 IO IO 5 OA0_OUT Op Amp0_OUT/ACMP0L+ / 24 6 RH0_A Digital Rheostat 0 Terminal A V 23 22 21 20 19 DDA 1 18 IO4 7 RH0_B Digital Rheostat 0 Terminal B AGND 2 17 IO3 8 RH1_A Digital Rheostat 1 Terminal A 9 RH1_B Digital Rheostat 1 Terminal B OA0- 3 16 IO2 10 SCL I2C_SCL OA0+ 4 15 IO1 11 SDA I2C_SDA 14 GPIO, ACMP0L-, ACMP1L-, EXT_OSC0_IN, OA0_OUT 5 GND 12 IO0 Vref0_Out or Temp_Sens_Out RH0_A 6 13 VDD 8 9 10 7 11 12 13 VDD Digital Power Supply 14 GND Digital Ground B L 0 _B _A A 0 1 1_ C D IO 15 IO1 GPIO, Chop_ACMP+, Vref1_OUT or S S Temp_Sens_Out, EXT_OSC1_IN or SLA_0 H H H R R R 16 IO2 GPIO, ACMP0L+, EXT_OSC2_IN, SLA_1
(Top View)
17 IO3 GPIO, AS_1_A, ACMP1L+ or SLA_2
STQFN-24
18 IO4 GPIO, AS_1_B, Chop_ACMP-or SLA_3 19 IO5 GPIO, AS_0_B 20 IO6 GPIO, AS_0_A, HD_Buff_Out, In Amp_Vref 21 I0 GPI, In Amp_OUT 22 OA1_OUT Op Amp1_OUT, ACMP1L+ 23 OA1+ Op Amp1 Non-inverting Input 24 OA1- Op Amp1 Inverting Input Legend:
ACMPx+
: ACMPx Positive Input
ACMPx-
: ACMPx Negative Input
SCL
: I2C Clock Input
SDA
: I2C Data Input/Output
Vrefx
: Voltage Reference Output
SLA:
Slave Address
Table 1: Functional Pin Description Pin No. Pin Signal Input Output Function Name Name Options Options STQFN 24L
1 VDDA VDDA Analog Power Supply -- -- 2 AGND AGND Analog Ground -- -- 3 OA0- OA0- Op Amp0 Inverting Input Analog -- 4 OA0+ OA0+ Op Amp0 Non-Inverting Input Analog -- OA0_OUT Op Amp0 Output -- Analog OA0_OUT 5 ACMP0L+ Analog Comparator 0 Positive In- put Analog -- 6 RH0_A RH0_A Digital Rheostat 0 Terminal A -- --
Datasheet Revision 2.1 13-Nov-2020
CFR0011-120-00 11 of 243 © 2020 Dialog Semiconductor Document Outline General Description Key Features Applications 1 Block Diagram 2 Pinout 2.1 Pin Configuration - STQFN-24L 3 Characteristics 3.1 Absolute Maximum Ratings 3.2 Electrostatic Discharge Ratings 3.3 Recommended Operating Conditions 3.4 Electrical Characteristics 3.5 Timing Characteristics 3.6 Oscillator Characteristics 3.6.1 OSC Power-On Delay 3.7 ACMP Characteristics 3.8 Internal Vref Characteristics 3.9 Output Buffers Characteristics 3.10 Analog Temperature Sensor Characteristics 3.11 Programmable Operational Amplifier Characteristics 3.12 100K Digital Rheostat Characteristics 3.13 Analog Switches Characteristics 4 User Programmability 5 IO Pins 5.1 GPIO Pins 5.2 GPI Pins 5.3 Pull-Up/Down Resistors 5.4 Fast Pull-Up/Down during Power-Up 5.5 I2C Mode IO Structure 5.5.1 I2C Mode Structure (for SCL and SDA) 5.6 Matrix OE IO Structure 5.7 GPI Structure 5.7.1 GPI Structure (for I0) 5.8 IO Pins Typical Performance 6 Connection Matrix 6.1 Matrix Input Table 6.2 Matrix Output Table 6.3 Connection Matrix Virtual Inputs 6.4 Connection Matrix Virtual Outputs 7 Combination Function Macrocells 7.1 2-Bit LUT or D Flip-Flop Macrocells 7.1.1 2-Bit LUT or D Flip-Flop Macrocell Used as 2-Bit LUT 7.1.2 Initial Polarity Operations 7.2 2-bit LUT or Programmable Pattern Generator 7.2.1 2-Bit LUT or PGen Macrocell Used as 2-Bit LUT 7.3 3-Bit LUT or D Flip-Flop with Set/Reset Macrocells 7.3.1 3-Bit LUT or D Flip-Flop Macrocells Used as 3-Bit LUTs 7.3.2 Initial Polarity Operations 7.4 4-Bit LUT or D Flip-Flop with Set/Reset Macrocell 7.4.1 4-Bit LUT Macrocell Used as 4-Bit LUT 7.5 3-Bit LUT or Pipe Delay/Ripple Counter Macrocell 7.5.1 3-Bit LUT or Pipe Delay Macrocells Used as 3-Bit LUT 8 Multi-Function Macrocells 8.1 3-Bit LUT or DFF/Latch with 8-Bit Counter/Delay Macrocells 8.1.1 3-Bit LUT or 8-Bit CNT/DLY Block Diagrams 8.1.2 3-Bit LUT or CNT/DLYs Used as 3-Bit LUTs 8.2 4-Bit LUT or DFF/Latch with 16-Bit Counter/Delay Macrocell 8.2.1 4-Bit LUT or DFF/LATCH with 16-Bit CNT/DLY Block Diagram 8.2.2 4-Bit LUT or 16-Bit Counter/Delay Macrocells Used as 4-Bit LUTs 8.3 CNT/DLY/FSM Timing Diagrams 8.3.1 Delay Mode CNT/DLY0 to CNT/DLY6 8.3.2 Count Mode (Count Data: 3), Counter Reset (Rising Edge Detect) CNT/DLY0 to CNT/DLY6 8.3.3 One-Shot Mode CNT/DLY0 to CNT/DLY6 8.3.4 Frequency Detection Mode CNT/DLY0 to CNT/DLY6 8.3.5 Edge Detection Mode CNT/DLY1 to CNT/DLY6 8.3.6 Delayed Edge Detection Mode CNT/DLY0 to CNT/DLY6 8.3.7 CNT/FSM Mode CNT/DLY0 8.3.8 Difference in Counter Value for Counter, Delay, One-Shot, and Frequency Detect Modes 8.4 Wake and Sleep Controller 9 Analog Comparators 9.1 Analog Comparators Overview 9.1.1 ACMP0L Block Diagram 9.1.2 ACMP1L Block Diagram 9.2 Chopper Analog Comparator 9.3 ACMP Sampling Mode 9.4 ACMP Typical Performance 10 Programmable Operational Amplifiers 10.1 General Description 10.2 Modes of Operation 10.2.1 Operational Amplifier Mode 10.2.2 Instrumentation Amplifier Mode 10.2.3 Analog Comparator Mode 10.2.4 Voltage Regulator Mode 10.2.5 Current Sink Mode 10.3 Op Amp Typical Performance 11 Analog Switch Macrocell 11.1 Analog Switch General Description 11.2 Half Bridge Mode 12 Digital Rheostats and Programmable Trim Block 12.1 Potentiometer Mode 12.2 Calculating Actual Resistance 12.3 Digital Rheostat Value Self-programming into the NVM 12.4 Trimming process Using Programmable Trim Block 12.4.1 Trimming Process with Auto-Trim Option Enabled 12.4.2 I2C Controlled Trimming Process with Auto-Trim Option Enabled 12.4.3 Changing Rheostat Value Directly via I2C 12.5 Using Chopper ACMP 13 Programmable Delay/Edge Detector 13.1 Programmable Delay Timing Diagram - Edge Detector Output 14 Additional Logic Function. Deglitch Filter 15 Voltage Reference 15.1 Voltage Reference Overview 15.2 Vref Selection Table 15.3 Vref Block Diagram 16 Clocking 16.1 OSC General Description 16.2 Oscillator0 (2.048 kHz) 16.3 Oscillator1 (2.048 MHz) 16.4 Oscillator2 (25 MHz) 16.5 CNT/DLY Clock Scheme 16.6 External Clocking 16.6.1 IO1 Source for Oscillator0 (2.048 kHz) 16.6.2 IO3 Source for Oscillator1 (2.048 MHz) 16.6.3 IO2 Source for Oscillator2 (25 MHz) 16.7 Oscillators Power-On Delay 16.8 Oscillators Accuracy 17 Power-On Reset 17.1 General Operation 17.2 POR Sequence 17.3 Macrocells Output States During POR Sequence 17.3.1 Initialization 17.3.2 Power-Down 18 I2C Serial Communications Macrocell 18.1 I2C Serial Communications Macrocell Overview 18.2 I2C Serial Communications Device Addressing 18.3 I2C Serial General Timing 18.4 I2C Serial Communications Commands 18.4.1 Byte Write Command 18.4.2 Sequential Write Command 18.4.3 Current Address Read Command 18.4.4 Random Read Command 18.4.5 Sequential Read Command 18.4.6 I2C Serial Reset Command 18.5 Chip Configuration Data Protection 18.6 I2C Serial Command Register Map 18.7 I2C Additional Options 18.7.1 Reading Counter Data via I2C 18.7.2 I2C Byte Write Bit Masking 19 Non-Volatile Memory 19.1 Serial NVM Write Operations 19.2 Serial NVM Read Operations 19.3 Serial NVM Erase Operations 19.4 Acknowledge Polling 19.5 Low power standby mode 19.6 Emulated EEPROM Write Protection 20 Analog Temperature Sensor 21 Register Definitions 21.1 Register Map 22 Package Top Marking System Definition 22.1 STQFN-24L 3 mm x 3 mm x 0.55 mm, 0.4P FCD Package 23 Package Information 23.1 Package outlines FOR STQFN 24L 3 mm x 3 mm x 0.55 mm 0.4P Green Package 23.2 STQFN Handling 23.3 Soldering Information 24 Ordering Information 24.1 Tape and Reel Specifications 25 Layout Guidelines 25.1 STQFN 24L 3 mm x 3 mm x 0.55 mm 0.4P Green Package Glossary Revision History