Datasheet ADPA7005CHIP (Analog Devices) - 19

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Data Sheet ADPA7005CHIP HMC980LP4E BIAS SEQUENCE T VDD
The dc supply sequencing in the Power-Up Sequence section
VDRAIN
and the Power-Down Sequence section is required to prevent damage to the HMC980LP4E when using it to control the
EN
ADPA7005CHIP.
1 Power-Up Sequence 3 VGATE
The power-up sequence is as follows: 1. VDIG = 3.3 V 2. S0 = 3.3 V 3. VDD = 5.68 V 4. VNEG = −1.5 V (unnecessary if using internally
CH1 2V CH2 1V M20.0ms
58 0 generated voltage)
CH3 2V CH4 2V A CH1 1.12V 50.00%
7319- 1 5. EN = 3.3 V (transition from 0 V to 3.3 V turns on VGATE Figure 58. Turn Off HMC980LP4E Outputs to ADPA7005CHIP and VDRAIN)
CONSTANT DRAIN CURRENT BIASING vs. Power-Down Sequence CONSTANT GATE VOLTAGE BIASING
The power-down sequence is as follows: The HMC980LP4E uses a closed-loop feedback to continuously 1. EN = 0 V (transition from 3.3 V to 0 V turns off VDRAIN adjust VGATE to maintain a constant gate current bias over dc and VGATE) supply variation, temperature, and part to part variation. In 2. VNEG = 0 V (unnecessary if using internally generated addition, constant drain current bias is the optimum method voltage) for reducing time in calibration procedures and for maintaining 3. VDD = 0 V consistent performance over time. By comparing with a constant 4. S0 = 0 V gate voltage bias where the current is driven to increase when RF 5. VDIG = 0 V power is applied, a slightly lower output P1dB is seen with a constant drain current bias. This output P1db is displayed in After the HMC980LP4E bias control circuit is set up, toggle Figure 62, where the RF performance is slightly lower than the bias to the ADPA7005CHIP on or off by applying 3.3 V or constant gate voltage bias operation due to a lower drain current at 0 V, respectively, to the EN pad. At EN = 3.3 V, VGATE drops to the high input powers as the device reaches 1 dB compression. −1.5 V and VDRAIN turns on at 5 V. VGATE then rises until IDRAIN = 800 mA, and the closed control loop regulates IDRAIN at The output P1dB performance for constant drain current bias 1600 mA. When EN = 0 V, VGATE is set to −1.5 V, and can be increased towards constant gate voltage bias VDRAIN is set to 0 V (see Figure 57 and Figure 58). performance by increasing the set current towards the IDD it would reach under RF drive in the constant gate voltage bias
T VDD
condition, as shown in Figure 62. The limit of increasing IDQ under the constant current operation is set by the thermal
VDRAIN EN
limitations that can be found in the absolute maximum ratings table (see Table 3) from the amplifier data sheet with the maximum power dissipation specification. As the IDD increase
1 3
continues, the actual output P1dB does not continue to increase
VGATE
indefinitely, and the power dissipation increases. Therefore, take the exchange between the power dissipation and output P1dB performance into consideration when using constant drain current biasing.
CH1 2V CH2 1V M20.0ms
57 0
CH3 2V CH4 2V A CH1 1.12V 50.00%
7319- 1 Figure 57. Turn On HMC980LP4E Outputs to ADPA7005CHIP Rev. 0 | Page 19 of 23 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS 20 GHz TO 34 GHz FREQUENCY RANGE 34 GHz TO 44 GHz FREQUENCY RANGE ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS INTERFACE SCHEMATICS TYPICAL PERFORMANCE CHARACTERISTIC CONSTANT IDD OPERATION THEORY OF OPERATION APPLICATIONS INFORMATION MOUNTING AND BONDING TECHNIQUES FOR MILLIMETERWAVE GaAs MMICS Handling Precautions Mounting Wire Bonding BIASING ADPA7005CHIP WITH THE HMC980LP4E APPLICATION CIRCUIT SETUP LIMITING VGATE FOR ADPA7005CHIP VGGx ABSOLUTE MAXIMUM RATING REQUIREMENT HMC980LP4E BIAS SEQUENCE Power-Up Sequence Power-Down Sequence CONSTANT DRAIN CURRENT BIASING vs. CONSTANT GATE VOLTAGE BIASING TYPICAL APPLICATION CIRCUIT ASSEMBLY DIAGRAM OUTLINE DIMENSIONS ORDERING GUIDE