Datasheet ADMV7710 (Analog Devices) - 5
| Manufacturer | Analog Devices |
| Description | 71 GHz to 76 GHz, 1 Watt E-Band Power Amplifier With Power Detector |
| Pages / Page | 18 / 5 — Data Sheet. ADMV7710. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. GG1. … |
| Revision | A |
| File Format / Size | PDF / 311 Kb |
| Document Language | English |
Data Sheet. ADMV7710. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. GG1. DD1A. GG2. DD2A. GG3. DD3A. GG4. DD4A. GND 20. RFOUT 21. GND. TOP VIEW
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Data Sheet ADMV7710 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 A A A A ND ND ND ND ND ND ND ND G G G G G G G G GG1 DD1A GG2 DD2A GG3 DD3A GG4 DD4A V V V V V V V V GND 20 RFOUT 21 GND 3 22 GND ADMV7710 TOP VIEW (Not to Scale) 2 RFIN 1 GND B B B B ET EF GG1 ND DD1B ND GG2 ND DD2B ND GG3 ND DD3B ND GG4 ND DD4B ND V G V G V G V G V G V G V G V G VD VR
002
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
16408- Figure 2. Pad Configuration
Table 4. Pad Function Descriptions Pad No. Mnemonic Description
1, 3, 5, 7, 9, 11, 13, GND Ground Connection (See Figure 3). 15, 17, 19, 20, 22, 25, 27, 29, 31, 33, 35, 37, 39 2 RFIN RF Input. AC-couple RFIN and match it to 50 Ω (see Figure 4). 4, 8, 12, 16 VGG1A to VGG4A First Stage Gate Bias Voltage for the Power Amplifier (See Figure 8). For the required external components, see Figure 47. 6, 10, 14, 18 VDD1A to VDD4A First Stage Drain Bias Voltage for the Power Amplifier (See Figure 5). 21 RFOUT RF Output. AC-couple RFOUT and match it to 50 Ω (see Figure 6). 23 VREF Reference Voltage for the Power Detector (See Figure 7). VREF is the dc bias of the diode biased through an external resistor used for temperature compensation of VDET. Refer to the typical application circuit (see Figure 47) for the required external components. 24 VDET Detector Voltage for the Power Detector (See Figure 7). VDET is the dc voltage representing the RF output power rectified by the diode, which is biased through an external resistor. Refer to the typical application circuit (see Figure 47) for the required external components. 26, 30, 34, 38 VDD4B to VDD1B Second Stage Drain Bias Voltage for the Power Amplifier (See Figure 5). 28, 32, 36, 40 VGG4B to VGG1B Second Stage Gate Bias Voltage for the Power Amplifier (See Figure 8). For the required external components, see Figure 47. Die Bottom GND Ground. The die bottom must be connected to the RF/dc ground (see Figure 3). Rev. A | Page 5 of 18 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS INTERFACE SCHEMATICS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION APPLICATIONS INFORMATION ASSEMBLY DIAGRAM MOUNTING AND BONDING TECHNIQUES FOR MILLIMETERWAVE GaAs MMICS HANDLING PRECAUTIONS Storage Cleanliness Static Sensitivity Transients General Handling MOUNTING Eutectic Die Attach Epoxy Die Attach WIRE BONDING OUTLINE DIMENSIONS ORDERING GUIDE
Data Sheet ADMV7710 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 A A A A ND ND ND ND ND ND ND ND G G G G G G G G GG1 DD1A GG2 DD2A GG3 DD3A GG4 DD4A V V V V V V V V GND 20 RFOUT 21 GND 3 22 GND ADMV7710 TOP VIEW (Not to Scale) 2 RFIN 1 GND B B B B ET EF GG1 ND DD1B ND GG2 ND DD2B ND GG3 ND DD3B ND GG4 ND DD4B ND V G V G V G V G V G V G V G V G VD VR
002
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
16408- Figure 2. Pad Configuration
Table 4. Pad Function Descriptions Pad No. Mnemonic Description
1, 3, 5, 7, 9, 11, 13, GND Ground Connection (See Figure 3). 15, 17, 19, 20, 22, 25, 27, 29, 31, 33, 35, 37, 39 2 RFIN RF Input. AC-couple RFIN and match it to 50 Ω (see Figure 4). 4, 8, 12, 16 VGG1A to VGG4A First Stage Gate Bias Voltage for the Power Amplifier (See Figure 8). For the required external components, see Figure 47. 6, 10, 14, 18 VDD1A to VDD4A First Stage Drain Bias Voltage for the Power Amplifier (See Figure 5). 21 RFOUT RF Output. AC-couple RFOUT and match it to 50 Ω (see Figure 6). 23 VREF Reference Voltage for the Power Detector (See Figure 7). VREF is the dc bias of the diode biased through an external resistor used for temperature compensation of VDET. Refer to the typical application circuit (see Figure 47) for the required external components. 24 VDET Detector Voltage for the Power Detector (See Figure 7). VDET is the dc voltage representing the RF output power rectified by the diode, which is biased through an external resistor. Refer to the typical application circuit (see Figure 47) for the required external components. 26, 30, 34, 38 VDD4B to VDD1B Second Stage Drain Bias Voltage for the Power Amplifier (See Figure 5). 28, 32, 36, 40 VGG4B to VGG1B Second Stage Gate Bias Voltage for the Power Amplifier (See Figure 8). For the required external components, see Figure 47. Die Bottom GND Ground. The die bottom must be connected to the RF/dc ground (see Figure 3). Rev. A | Page 5 of 18 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS INTERFACE SCHEMATICS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION APPLICATIONS INFORMATION ASSEMBLY DIAGRAM MOUNTING AND BONDING TECHNIQUES FOR MILLIMETERWAVE GaAs MMICS HANDLING PRECAUTIONS Storage Cleanliness Static Sensitivity Transients General Handling MOUNTING Eutectic Die Attach Epoxy Die Attach WIRE BONDING OUTLINE DIMENSIONS ORDERING GUIDE
