Datasheet AD8488 (Analog Devices) - 17
| Manufacturer | Analog Devices |
| Description | 128-Channel Digital X-Ray Analog Front End |
| Pages / Page | 20 / 17 — Data Sheet. AD8488. TIMING DIAGRAMS. CS_A, CS_B. DATA |
| Revision | A |
| File Format / Size | PDF / 359 Kb |
| Document Language | English |
Data Sheet. AD8488. TIMING DIAGRAMS. CS_A, CS_B. DATA
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Text Version of Document
Data Sheet AD8488 TIMING DIAGRAMS CS_A, CS_B t1 t2 t4 t3 WR t5 t6 DATA NOTES 1. TIMING DIAGRAM TO WRITE A STATIC SIGNAL TO CHANNEL 0 TO CHANNEL 63 OR CHANNEL 64 TO CHANNEL127.
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2. CS_A LOW OR CS_B LOW SELECTS CHANNEL 0 TO CHANNEL 63 OR CHANNEL 64 TO CHANNEL 127. WRITE DATA BY SEQUENCING WR LOW, THEN HIGH.
09801- Figure 18. Input Register Timing Diagram
tCLK CLK MUX-CH001 tDELAY7 TO MUX-CH003 001 tDELAY8 002 003 ADC INPUT SAMPLE ADC SAMPLE ADC SAMPLE ADC SAMPLE SETTLES MUX-CH001 MUX-CH002 MUX-CH003 NOTES 1. ADC SAMPLES OCCUR WHEN MUX-CH001 TO MUX-CH003 IS HIGH, JUST PRIOR TO THE FALLING EDGE. SAMPLE MUST BE COMPLETE BEFORE HIGH TO LOW TRANSITION. 2. TIME DELAY SAMPLES (REFERENCE, INTERNAL ONLY): MIN. TYP. MAX. tDELAY 7: 5.3ns 6.6ns 7.8ns tDELAY 8: 1.2ns 1.4ns 1.7ns
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3. tA IS SYNCHRONOUS WITH ADC TIMING.
09801- Figure 19. Timing Diagram—AD8488 to ADC Rev. A | Page 17 of 20 Document Outline Features Application General Description Functional Block Diagram Table of Contents Revision History Specifications Absolute Maximum Ratings Thermal Data Thermal Characterization ESD Caution Pin Configuration and Function Descriptions Signal Mnemonics Typical Performance Characteristics Theory of Operation Overview Analog Amplifier Troubleshooting Channels Timing Signals Timing Notes Applications Information Control Register Bit Maps Timing Diagrams Outline Dimensions Ordering Guide
019
2. CS_A LOW OR CS_B LOW SELECTS CHANNEL 0 TO CHANNEL 63 OR CHANNEL 64 TO CHANNEL 127. WRITE DATA BY SEQUENCING WR LOW, THEN HIGH.
09801- Figure 18. Input Register Timing Diagram
tCLK CLK MUX-CH001 tDELAY7 TO MUX-CH003 001 tDELAY8 002 003 ADC INPUT SAMPLE ADC SAMPLE ADC SAMPLE ADC SAMPLE SETTLES MUX-CH001 MUX-CH002 MUX-CH003 NOTES 1. ADC SAMPLES OCCUR WHEN MUX-CH001 TO MUX-CH003 IS HIGH, JUST PRIOR TO THE FALLING EDGE. SAMPLE MUST BE COMPLETE BEFORE HIGH TO LOW TRANSITION. 2. TIME DELAY SAMPLES (REFERENCE, INTERNAL ONLY): MIN. TYP. MAX. tDELAY 7: 5.3ns 6.6ns 7.8ns tDELAY 8: 1.2ns 1.4ns 1.7ns
020
3. tA IS SYNCHRONOUS WITH ADC TIMING.
09801- Figure 19. Timing Diagram—AD8488 to ADC Rev. A | Page 17 of 20 Document Outline Features Application General Description Functional Block Diagram Table of Contents Revision History Specifications Absolute Maximum Ratings Thermal Data Thermal Characterization ESD Caution Pin Configuration and Function Descriptions Signal Mnemonics Typical Performance Characteristics Theory of Operation Overview Analog Amplifier Troubleshooting Channels Timing Signals Timing Notes Applications Information Control Register Bit Maps Timing Diagrams Outline Dimensions Ordering Guide
