Datasheet AD5522 (Analog Devices) - 60

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AD5522 Data Sheet Table 39. ADCs and ADC Drivers Suggested For Use with AD55221 Sample Part No. Resolution Rate Ch. No. AIN Range Interface ADC Driver Multiplexer2 Package
AD7685 16 250 kSPS 1 0 V to VREF Serial, SPI ADA4841-1, ADG704, ADG708 MSOP, ADA4841-2 LFCSP AD7686 16 500 kSPS 1 0 V to VREF Serial, SPI ADA4841-1, ADG704, ADG708 MSOP, ADA4841-2 LFCSP AD76933 16 500 kSPS 1 −VREF to +VREF Serial, SPI ADA4841-1, ADG1404, ADG1408, MSOP, ADA4841-2, ADG1204 LFCSP ADA4941-1 AD7610 16 250 kSPS 1 Bipolar 10 V, Bipolar Serial/Parallel AD8021 ADG1404, ADG1408, LFCSP, 5 V, Unipolar 10 V, ADG1204 LQFP Unipolar 5 V AD7655 16 1 MSPS 4 0 V to 5 V Serial/Parallel ADA4841-1, ADA4841-2, AD8021 1 Subset of the possible ADCs suitable for use with the AD5522. Visit www.analog.com for more options. 2 For purposes of sharing an ADC among multiple PMU channels. Note that the multiplexer is not absolutely necessary because the AD5522 MEASOUTx path has a tri- state mode per channel. 3 Do not allow the MEASOUTx output range to exceed the analog input (AIN) range of the ADC.
POWER SUPPLY DECOUPLING
shielded with digital ground to avoid radiating noise to other Careful consideration of the power supply and ground return parts of the board, and they should never be run near the refer- layout helps to ensure the rated performance. Design the ence inputs. It is essential to minimize noise on all VREF lines. printed circuit board (PCB) on which the AD5522 is mounted Avoid crossover of digital and analog signals. Traces on opposite so that the analog and digital sections are separated and sides of the board should run at right angles to each other to confined to certain areas of the board. If the AD5522 is in a reduce the effects of feedthrough through the board. As is the system where multiple devices require an AGND-to-DGND case for all thin packages, care must be taken to avoid flexing connection, the connection should be made at one point only. the package and to avoid a point load on the surface of this Establish the star ground point as close as possible to the device. package during the assembly process. For supplies with multiple pins (AVSS and AVDD), it is Also, note that the exposed paddle of the AD5522 is connected recommended that these pins be tied together and that each to the negative supply, AVSS. supply be decoupled only once.
POWER SUPPLY SEQUENCING
The AD5522 should have ample supply decoupling of 10 μF in When the supplies are connected to the AD5522, it is important parallel with 0.1 μF on each supply located as close to the that the AGND and DGND pins be connected to the relevant package as possible, ideally right up against the device. The ground planes before the positive or negative supplies are applied. 10 μF capacitors are the tantalum bead type. The 0.1 μF capac- This is the only power sequencing requirement for this device. itors should have low effective series resistance (ESR) and low effective series inductance (ESL)—typical of the common
TYPICAL APPLICATION FOR THE AD5522
ceramic types that provide a low impedance path to ground at Figure 59 shows the AD5522 used in an ATE system. The device high frequencies—to handle transient currents due to internal can be used as a per-pin parametric unit to speed up the rate at logic switching. which testing can be done. Avoid running digital lines under the device because they can The central PMU (shown in the block diagram) is usually a couple noise onto the device. However, allow the analog ground highly accurate PMU and is shared among a number of pins in plane to run under the AD5522 to avoid noise coupling (applies the tester. In general, many discrete levels are required in an only to the package with paddle up). The power supply lines of ATE system for the pin drivers, comparators, clamps, and active the AD5522 should use as large a trace as possible to provide loads. DAC devices such as the AD537x family offer a highly low impedance paths and reduce the effects of glitches on the integrated solution for a number of these levels. power supply line. Fast switching digital signals should be Rev. F | Page 60 of 64 Document Outline Features Applications Functional Block Diagram Revision History General Description Specifications Timing Characteristics Circuit and Timing Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Terminology Theory of Operation Force Amplifier Comparators Clamps Current Range Selection High Current Ranges Measure Current Gains VMID Voltage Choosing Power Supply Rails Measure Output (MEASOUTx Pins) Device Under Test Ground (DUTGND) Guard Amplifier Compensation Capacitors System Force and Sense Switches Temperature Sensor DAC Levels Offset DAC Gain and Offset Registers Cached X2 Registers Gain and Offset Registers for the FIN DAC Gain and Offset Registers for the Comparator DACs Gain and Offset Registers for the Clamp DACs Reference Voltage (VREF) Reference Selection Reference Selection Example Calibration Reducing Zero-Scale Error Reducing Gain Error Calibration Example Additional Calibration System Level Calibration Circuit Operation Force Voltage (FV) Mode Force Current (FI) Mode Serial Interface SPI Interface LVDS Interface Serial Interface Write Mode RESETB Function BUSYB and LOADB Functions Register Update Rates Register Selection Readback Control, RD/WRB PMU Address Bits: PMU3, PMU2, PMU1, PMU0 NOP (No Operation) Reserved Commands Write System Control Register Write PMU Register Write DAC Register DAC Addressing Read Registers Readback of System Control Register Readback of PMU Register Readback of Comparator Status Register Readback of Alarm Status Register Readback of DAC Register Applications Information Power-On Default Setting Up the Device on Power-On Changing Modes Required External Components Power Supply Decoupling Power Supply Sequencing Typical Application for the AD5522 Outline Dimensions Ordering Guide