Datasheet ADP5014 (Analog Devices) - 31
| Manufacturer | Analog Devices |
| Description | Integrated Power Solution with Quad Low Noise Buck Regulators |
| Pages / Page | 34 / 31 — Data Sheet. ADP5014. TYPICAL APPLICATION CIRCUITS. VREF 0.47µF. OSC. REF. … |
| Revision | A |
| File Format / Size | PDF / 840 Kb |
| Document Language | English |
Data Sheet. ADP5014. TYPICAL APPLICATION CIRCUITS. VREF 0.47µF. OSC. REF. 82.5kΩ. VREF. EN1/ENALL. CFG1. EN2/DL12. CFG2. 31.6kΩ. LOGIC DECODER
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Text Version of Document
Data Sheet ADP5014 TYPICAL APPLICATION CIRCUITS ADP5014 VREF 0.47µF RT OSC REF 82.5kΩ VREF EN1/ENALL CFG1 0Ω EN2/DL12 CFG2 0Ω 31.6kΩ LOGIC DECODER EN3/UV EN4/DL34 GPIO 26.1kΩ AVIN FB1 5.0V PVIN1 PVIN1 C1 C2 SW1 10µF 1µF CH 1 L1 VOUT1 1.2V/4A BUCK VCORE VREF (2A/4A) SW1 0.8µH VSET1 C3 13.3kΩ C4 C5 PGND1 47µF 47µF 47µF 20kΩ COMP1 FPGA PGND1 20kΩ 10nF 4.32kΩ FB2 PVIN2 4.99kΩ C6 SW2 AUXILIARY 10µF VOLTAGE PVIN2 CH 2 L2 BUCK VOUT2 2.5V/2A VREF VSET2 (2A/4A) SW2 0.8µH C7 C8 BANK 0 PGND2 47µF 47µF I/Os BANK 1 BANK 2 COMP2 PGND2 10nF 4.32kΩ PVIN3 L3 SW3 VOUT3 1.5V/2A C9 I/Os BANK 3 1.5µH 10µF CH 3 FB3 C10 47µF BUCK VREF 6.65kΩ VSET3 (1A/2A) PGND3 DDR DDR3 MEMORY 20kΩ TERM. LDO COMP3 10nF 4.32kΩ PVIN4 L4 SW4 VOUT4 3.3V/2A FLASH MEMORY C11 1.5µH 10µF FB4 C12 CH 4 47µF VREF VSET4 BUCK 13kΩ (1A/2A) 20kΩ PGND4 COMP4 10nF 6.04kΩ AGND EXPOSED PAD ENALL 2ms 1.2V 36ms 6ms 2.5V/1.5V 24ms 3.3V 12ms 12ms
047 15496- Figure 46. Typical Field Programmable Gate Array (FPGA) Application, 1.2 MHz Switching Frequency, Sequence Enable Mode Rev. A | Page 31 of 34 Document Outline FEATURES APPLICATIONS TYPICAL APPLICATION CIRCUIT GENERAL DESCRIPTION REVISION HISTORY DETAILED FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS BUCK REGULATOR SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION BUCK REGULATOR OPERATIONAL MODES PWM Mode PSM Mode FPWM and Automatic PWM/PSM Modes LOW NOISE ARCHITECTURE INTERNAL REFERENCE (VREF) ADJUSTABLE OUTPUT VOLTAGE FUNCTION CONFIGURATIONS (CFG1 AND CFG2) PARALLEL OPERATION MANUAL/SEQUENCE MODE Manual Mode (Precision Enable) Sequence Mode GENERAL PURPOSE INPUT/OUTPUT (GPIO) OSCILLATOR Phase Shift SYNCHRONIZATION INPUT/OUTPUT POWER-GOOD FUNCTION UV COMPARATOR (SEQUENCE MODE ONLY) SOFT START STARTUP WITH PRECHARGED OUTPUT CURRENT-LIMIT PROTECTION FREQUENCY FOLD BACK SHORT-CIRCUIT PROTECTION (SCP) OVERVOLTAGE PROTECTION UNDERVOLTAGE LOCKOUT ACTIVE OUTPUT DISCHARGE SWITCH THERMAL SHUTDOWN APPLICATIONS INFORMATION ADIsimPOWER DESIGN TOOL PROGRAMMING THE OUTPUT VOLTAGE VOLTAGE CONVERSION LIMITATIONS CURRENT-LIMIT SETTING SOFT START SETTING INDUCTOR SELECTION OUTPUT CAPACITOR SELECTION INPUT CAPACITOR SELECTION PROGRAMMING THE UVLO INPUT COMPENSATION COMPONENTS DESIGN POWER DISSIPATION Buck Regulator Power Dissipation Power Switch Conduction Loss (PCOND) Switching Loss (PSW) Transition Loss (PTRAN) Thermal Shutdown JUNCTION TEMPERATURE DESIGN EXAMPLES SETTING THE SWITCHING FREQUENCY SETTING THE OUTPUT VOLTAGE SETTING THE CONFIGUATIONS (CFG1 AND CFG2) SELECTING THE INDUCTOR SELECTING THE OUTPUT CAPACITOR DESIGNING THE COMPENSATION NETWORK LOW NOISE OUTPUT DESIGN PCB LAYOUT RECOMMENDATIONS TYPICAL APPLICATION CIRCUITS FACTORY PROGRAMMABLE OPTIONS FACTORY DEFAULT OPTIONS OUTLINE DIMENSIONS ORDERING GUIDE
047 15496- Figure 46. Typical Field Programmable Gate Array (FPGA) Application, 1.2 MHz Switching Frequency, Sequence Enable Mode Rev. A | Page 31 of 34 Document Outline FEATURES APPLICATIONS TYPICAL APPLICATION CIRCUIT GENERAL DESCRIPTION REVISION HISTORY DETAILED FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS BUCK REGULATOR SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION BUCK REGULATOR OPERATIONAL MODES PWM Mode PSM Mode FPWM and Automatic PWM/PSM Modes LOW NOISE ARCHITECTURE INTERNAL REFERENCE (VREF) ADJUSTABLE OUTPUT VOLTAGE FUNCTION CONFIGURATIONS (CFG1 AND CFG2) PARALLEL OPERATION MANUAL/SEQUENCE MODE Manual Mode (Precision Enable) Sequence Mode GENERAL PURPOSE INPUT/OUTPUT (GPIO) OSCILLATOR Phase Shift SYNCHRONIZATION INPUT/OUTPUT POWER-GOOD FUNCTION UV COMPARATOR (SEQUENCE MODE ONLY) SOFT START STARTUP WITH PRECHARGED OUTPUT CURRENT-LIMIT PROTECTION FREQUENCY FOLD BACK SHORT-CIRCUIT PROTECTION (SCP) OVERVOLTAGE PROTECTION UNDERVOLTAGE LOCKOUT ACTIVE OUTPUT DISCHARGE SWITCH THERMAL SHUTDOWN APPLICATIONS INFORMATION ADIsimPOWER DESIGN TOOL PROGRAMMING THE OUTPUT VOLTAGE VOLTAGE CONVERSION LIMITATIONS CURRENT-LIMIT SETTING SOFT START SETTING INDUCTOR SELECTION OUTPUT CAPACITOR SELECTION INPUT CAPACITOR SELECTION PROGRAMMING THE UVLO INPUT COMPENSATION COMPONENTS DESIGN POWER DISSIPATION Buck Regulator Power Dissipation Power Switch Conduction Loss (PCOND) Switching Loss (PSW) Transition Loss (PTRAN) Thermal Shutdown JUNCTION TEMPERATURE DESIGN EXAMPLES SETTING THE SWITCHING FREQUENCY SETTING THE OUTPUT VOLTAGE SETTING THE CONFIGUATIONS (CFG1 AND CFG2) SELECTING THE INDUCTOR SELECTING THE OUTPUT CAPACITOR DESIGNING THE COMPENSATION NETWORK LOW NOISE OUTPUT DESIGN PCB LAYOUT RECOMMENDATIONS TYPICAL APPLICATION CIRCUITS FACTORY PROGRAMMABLE OPTIONS FACTORY DEFAULT OPTIONS OUTLINE DIMENSIONS ORDERING GUIDE