Datasheet ADP5054 (Analog Devices) - 21

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Data Sheet ADP5054 APPLICATIONS INFORMATION ADIsimPOWER DESIGN TOOL
The minimum output voltage in FPWM mode for a given input The ADP5054 is supported by the ADIsimPower™ design tool voltage and switching frequency can be calculated using the set. ADIsimPower is a collection of tools that produces complete following equation: power designs optimized for a specific design goal. The tools VOUT_MIN = VIN × tMIN_ON × fSW − (RDSON1 − RDSON2) × enable the user to generate a full schematic and bill of materials IOUT_MIN × tMIN_ON × fSW − (RDSON2 + RL) × IOUT_MIN (1) and to calculate performance in minutes. ADIsimPower can where: optimize designs for cost, area, efficiency, and part count while VOUT_MIN is the minimum output voltage. taking into consideration the operating conditions and limitations tMIN_ON is the minimum on time. of the IC and all real external components. The ADIsimPower fSW is the switching frequency. tool can be found at www.analog.com/ADIsimPower; the user RDSON1 is the high-side MOSFET on resistance. can request an unpopulated board through the tool. RDSON2 is the low-side MOSFET on resistance.
PROGRAMMING THE OUTPUT VOLTAGE
IOUT_MIN is the minimum output current. R The output voltage of the ADP5054 is externally set by a L is the resistance of the output inductor. resistive voltage divider from the output voltage to the FBx pin. The maximum output voltage for a given input voltage and To limit the degradation of the output voltage accuracy due to FBx switching frequency is limited by the minimum off time and bias current, ensure that the bottom resistor in the divider is not the maximum duty cycle. Note that the frequency foldback too large; a value of less than 200 kΩ is recommended. feature helps to increase the effective maximum duty cycle by lowering the switching frequency, thereby decreasing the The equation for the output voltage setting is dropout voltage between the input and output voltages (see VOUT = VREF × (1 + (RTOP/RBOT)) the Frequency Foldback section). where: The maximum output voltage for a given input voltage and VOUT is the output voltage. switching frequency can be calculated using the following equation: VREF is the 0.8 V feedback reference voltage. V R OUT_MAX = VIN × (1 − tMIN_OFF × fSW) − (RDSON1 − RDSON2) × TOP is the feedback resistor from VOUT to FBx. I R OUT_MAX × (1 − tMIN_OFF × fSW) − (RDSON2 + RL) × IOUT_MAX (2) BOT is the feedback resistor from FBx to ground. where: No resistor divider is required in the fixed output options. Each V channel can be programmed to have a specific output voltage OUT_MAX is the maximum output voltage. t over a specific range. If a different fixed output voltage is MIN_OFF is the minimum off time. f required, contact your local Analog Devices sales or SW is the switching frequency. R distribution representative. DSON1 is the high-side MOSFET on resistance. RDSON2 is the low-side MOSFET on resistance.
VOLTAGE CONVERSION LIMITATIONS
IOUT_MAX is the maximum output current. For a given input voltage, upper and lower limitations on the RL is the resistance of the output inductor. output voltage exist due to the minimum on time and the As shown in Equation 1 and Equation 2, reducing the switching minimum off time. frequency eases the minimum on time and minimum off time The minimum output voltage for a given input voltage and limitations. switching frequency is limited by the minimum on time. The
CURRENT-LIMIT SETTING
minimum on time for Channel 1 and Channel 2 is 115 ns The ADP5054 has three selectable current-limit thresholds for (typical); the minimum on time for Channel 3 and Channel 4 Channel 1 and Channel 2. Ensure that the selected current-limit is 95 ns (typical). The minimum on time increases at higher value is larger than the peak current of the inductor, I junction temperatures. PEAK. See Table 10 for the current-limit configurations for Channel 1 and Note that in forced PWM mode, Channel 1 and Channel 2 can Channel 2. potentially exceed the nominal output voltage when the minimum on time limit is exceeded. Careful switching frequency selection is required to avoid this problem. Rev. G | Page 21 of 31 Document Outline FEATURES APPLICATIONS TYPICAL APPLICATION CIRCUIT GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY DETAILED FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS BUCK REGULATOR SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION BUCK REGULATOR OPERATIONAL MODES PWM Mode PSM Mode Forced PWM and Automatic PWM/PSM Modes ADJUSTABLE AND FIXED OUTPUT VOLTAGE INTERNAL REGULATORS (VREG AND VDD) SEPARATE SUPPLY APPLICATIONS LOW-SIDE DEVICE SELECTION BOOTSTRAP CIRCUITRY ACTIVE OUTPUT DISCHARGE SWITCH PRECISION ENABLING OSCILLATOR Phase Shift SYNCHRONIZATION INPUT/OUTPUT SOFT START PARALLEL OPERATION STARTUP WITH PRECHARGED OUTPUT CURRENT-LIMIT PROTECTION FREQUENCY FOLDBACK PULSE SKIP IN MAXIMUM DUTY SHORT-CIRCUIT PROTECTION (SCP) LATCH-OFF PROTECTION Short-Circuit Latch-Off Mode UNDERVOLTAGE LOCKOUT (UVLO) POWER-GOOD FUNCTION THERMAL SHUTDOWN APPLICATIONS INFORMATION ADIsimPOWER DESIGN TOOL PROGRAMMING THE OUTPUT VOLTAGE VOLTAGE CONVERSION LIMITATIONS CURRENT-LIMIT SETTING SOFT START SETTING INDUCTOR SELECTION OUTPUT CAPACITOR SELECTION INPUT CAPACITOR SELECTION LOW-SIDE POWER DEVICE SELECTION PROGRAMMING THE UVLO INPUT COMPENSATION COMPONENTS DESIGN POWER DISSIPATION Buck Regulator Power Dissipation Power Switch Conduction Loss (PCOND) Switching Loss (PSW) Transition Loss (PTRAN) Thermal Shutdown JUNCTION TEMPERATURE DESIGN EXAMPLES SETTING THE SWITCHING FREQUENCY SETTING THE OUTPUT VOLTAGE SETTING THE CURRENT LIMIT SELECTING THE INDUCTOR SELECTING THE OUTPUT CAPACITOR SELECTING THE LOW-SIDE MOSFET DESIGNING THE COMPENSATION NETWORK SELECTING THE SOFT START TIME SELECTING THE INPUT CAPACITOR PRINTED CIRCUIT BOARD LAYOUT RECOMMENDATIONS TYPICAL APPLICATION CIRCUIT FACTORY DEFAULT OPTIONS OUTLINE DIMENSIONS ORDERING GUIDE