Datasheet ADP5054 (Analog Devices) - 22

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ADP5054 Data Sheet SOFT START SETTING Table 11. Recommended Inductors
The buck regulators in the ADP5054 include soft start circuitry
Value ISAT IRMS DCR Size Vendor Part No. (μH) (A) (A) (mΩ) (mm)
that ramps the output voltage in a controlled manner during Coilcraft XFL4030-332 3.3 5.5 6.6 26 4 × 4 startup, thereby limiting the inrush current. To set the soft start XFL4030-472 4.7 4.5 5.1 40.1 4 × 4 time to a value of 2 ms or 16 ms, connect a resistor divider from XFL4030-682 6.8 3.6 3.9 67.4 4 × 4 the CFG12 pin or the CFG34 pin to the VREG pin and ground XFL5030-801 0.8 18.5 13 5.14 5 × 5 (see the Soft Start section). XAL5030-122 1.2 12.5 11.1 8.5 5 ×5
INDUCTOR SELECTION
XAL5030-222 2.2 9.2 9.7 13.2 5× 5 XAL5030-332 3.3 8.7 8.1 21.2 5 × 5 The inductor value is determined by the operating frequency, XAL5030-472 4.7 6.7 5.9 36 5 × 5 input voltage, output voltage, and inductor ripple current. Using TOKO FDV0530-1R0 1.0 11.2 9.1 9.4 6.2 × 5.8 a small inductor yields faster transient response but degrades FDV0530-2R2 2.2 7.1 7.0 17.3 6.2 × 5.8 efficiency due to the larger inductor ripple current. Using a FDV0530-3R3 3.3 5.5 5.3 29.6 6.2 × 5.8 large inductor value yields a smaller ripple current and better FDV0530-4R7 4.7 4.6 4.2 46.6 6.2 × 5.8 efficiency but results in slower transient response. Thus, a WE-HCI 744314076 0.76 15 15.5 2.25 7 × 7 trade-off must be made between transient response and 744314110 1.1 13 15 3.15 7 × 7 efficiency. As a guideline, the inductor ripple current, ΔIL, is 744314200 2.0 9 11.5 5.85 7 × 7 typically set to a value from 30% to 40% of the maximum load 744311330 3.3 8 9.0 9.0 7 × 7 current. The inductor value can be calculated using the following equation:
OUTPUT CAPACITOR SELECTION
L = ((VIN − VOUT) × D)/(ΔIL × fSW) The selected output capacitor affects both the output voltage where: ripple and the loop dynamics of the regulator. For example, V during load step transients on the output, when the load is IN is the input voltage. V suddenly increased, the output capacitor supplies the load until OUT is the output voltage. D is the duty cycle (D = V the control loop can ramp up the inductor current, causing an OUT/VIN). ΔI undershoot of the output voltage. L is the inductor ripple current. fSW is the switching frequency. The output capacitance required to meet the voltage drop. The ADP5054 has internal slope compensation in the current requirement can be calculated using the following equation: loop to prevent subharmonic oscillations when the duty cycle K  I 2  L UV STEP  is greater than 50%. COUT _UV 2  V  V  V IN OUT  OUT _ UV The inductor peak current is calculated using the following where: equation: KUV is a factor (typically set to 2). IPEAK = IOUT + (ΔIL/2) ΔISTEP is the load step. The saturation current of the inductor must be larger than the L is the output inductor. peak inductor current. For ferrite core inductors with a fast ΔVOUT_UV is the allowable undershoot on the output voltage. saturation characteristic, the saturation current rating of the Another example of the effect of the output capacitor on the inductor must be higher than the current-limit threshold of the loop dynamics of the regulator is when the load is suddenly buck regulator to prevent the inductor from becoming saturated. removed from the output and the energy stored in the inductor The rms current of the inductor can be calculated using the rushes into the output capacitor, causing an overshoot of the following equation: output voltage. 2  The output capacitance required to meet the overshoot I 2 L I  I  RMS OUT requirement can be calculated using the following equation: 12 2 K  I  L Shielded ferrite core materials are recommended for low core OV STEP C  OUT _ OV V  V  V OUT OUT_OV 2 2 loss and low electromagnetic interference (EMI). Table 11 lists OUT the recommended inductors. where: KOV is a factor (typically set to 2). ΔI STEP is the load step. ΔVOUT_OV is the allowable overshoot on the output voltage. Rev. G | Page 22 of 31 Document Outline FEATURES APPLICATIONS TYPICAL APPLICATION CIRCUIT GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY DETAILED FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS BUCK REGULATOR SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION BUCK REGULATOR OPERATIONAL MODES PWM Mode PSM Mode Forced PWM and Automatic PWM/PSM Modes ADJUSTABLE AND FIXED OUTPUT VOLTAGE INTERNAL REGULATORS (VREG AND VDD) SEPARATE SUPPLY APPLICATIONS LOW-SIDE DEVICE SELECTION BOOTSTRAP CIRCUITRY ACTIVE OUTPUT DISCHARGE SWITCH PRECISION ENABLING OSCILLATOR Phase Shift SYNCHRONIZATION INPUT/OUTPUT SOFT START PARALLEL OPERATION STARTUP WITH PRECHARGED OUTPUT CURRENT-LIMIT PROTECTION FREQUENCY FOLDBACK PULSE SKIP IN MAXIMUM DUTY SHORT-CIRCUIT PROTECTION (SCP) LATCH-OFF PROTECTION Short-Circuit Latch-Off Mode UNDERVOLTAGE LOCKOUT (UVLO) POWER-GOOD FUNCTION THERMAL SHUTDOWN APPLICATIONS INFORMATION ADIsimPOWER DESIGN TOOL PROGRAMMING THE OUTPUT VOLTAGE VOLTAGE CONVERSION LIMITATIONS CURRENT-LIMIT SETTING SOFT START SETTING INDUCTOR SELECTION OUTPUT CAPACITOR SELECTION INPUT CAPACITOR SELECTION LOW-SIDE POWER DEVICE SELECTION PROGRAMMING THE UVLO INPUT COMPENSATION COMPONENTS DESIGN POWER DISSIPATION Buck Regulator Power Dissipation Power Switch Conduction Loss (PCOND) Switching Loss (PSW) Transition Loss (PTRAN) Thermal Shutdown JUNCTION TEMPERATURE DESIGN EXAMPLES SETTING THE SWITCHING FREQUENCY SETTING THE OUTPUT VOLTAGE SETTING THE CURRENT LIMIT SELECTING THE INDUCTOR SELECTING THE OUTPUT CAPACITOR SELECTING THE LOW-SIDE MOSFET DESIGNING THE COMPENSATION NETWORK SELECTING THE SOFT START TIME SELECTING THE INPUT CAPACITOR PRINTED CIRCUIT BOARD LAYOUT RECOMMENDATIONS TYPICAL APPLICATION CIRCUIT FACTORY DEFAULT OPTIONS OUTLINE DIMENSIONS ORDERING GUIDE