Datasheet ADSP-BF700, 701, 702, 703, 704, 705, 706, 707 (Analog Devices) - 16

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ADSP-BF700/701/702/703/704/705/706/707 ADSP-BF706 EZ-KIT Mini Designing an Emulator-Compatible DSP Board (Target)
The ADSP-BF706 EZ-KIT MiniTM product (ADZS-BF706- For embedded system test and debug, Analog Devices provides EZMini) contains the ADSP-BF706 processor and is shipped a family of emulators. On each DAP-enabled processor, Analog with all of the necessary hardware. Users can start their evalua- Devices supplies an IEEE 1149.1 JTAG test access port (TAP), tion immediately. The EZ-KIT Mini product includes the serial wire debug port (SWJ-DP), and trace capabilities.  standalone evaluation board and USB cable. The EZ-KIT Mini In-circuit emulation is facilitated by use of the JTAG or SWD ships with an on-board debug agent. interface. The emulator accesses the processor’s internal fea- The evaluation board is designed to be used in conjunction with tures through the processor’s TAP, allowing the developer to the CrossCore Embedded Studio (CCES) development tools to load code, set breakpoints, and view variables, memory, and test capabilities of the ADSP-BF706 Blackfin processor. registers. The emulators require the target board to include a header(s) that supports connection of the processor’s DAP to
Blackfin Low Power Imaging Platform (BLIP)
the emulator for trace and debug. The Blackfin low power imaging platform (BLIP) integrates the Analog Devices emulators actively drive JTG_TRST high. ADSP-BF707 Blackfin processor and Analog Devices software Third-party emulators may expect a pull-up on JTG_TRST and code libraries. The code libraries are optimized to detect the therefore will not drive JTG_TRST high. When using this type presence and behavior of humans or vehicles in indoor and out- of third-party emulator JTG_TRST must still be driven low door environments. The BLIP hardware platform is delivered during power-up reset, but should subsequently be driven high preloaded with the occupancy software module. externally before any emulation or boundary-scan operations. See Power-Up Reset Timing for more information on POR
Software Add-Ins for CrossCore Embedded Studio
specifications. Analog Devices offers software add-ins which seamlessly inte- For more details on target board design issues including grate with CrossCore Embedded Studio to extend its capabilities mechanical layout, single processor connections, signal buffer- and reduce development time. Add-ins include board support ing, signal termination, and emulator pod logic, contact the packages for evaluation hardware, various middleware pack- factory for more information. ages, and algorithmic modules. Documentation, help, configuration dialogs, and coding examples present in these
ADDITIONAL INFORMATION
add-ins are viewable through the CrossCore Embedded Studio The following publications that describe the ADSP-BF70x pro- IDE once the add-in is installed. cessors can be accessed electronically on our website:
Board Support Packages for Evaluation Hardware
• ADSP-BF70x Blackfin+ Processor Hardware Reference Software support for the EZ-KIT Lite evaluation boards and EZ- • ADSP-BF70x Blackfin+ Processor Programming Reference Extender daughter cards is provided by software add-ins called • ADSP-BF70x Blackfin+ Processor Anomaly List board support packages (BSPs). The BSPs contain the required drivers, pertinent release notes, and select example code for the
RELATED SIGNAL CHAINS
given evaluation hardware. A download link for a specific BSP is located on the web page for the associated EZ-KIT or EZ- A signal chain is a series of signal-conditioning electronic com- Extender product. The link is found in the Product Download ponents that receive input (data acquired from sampling either area of the product web page. real-time phenomena or from stored data) in tandem, with the output of one portion of the chain supplying input to the next.
Middleware Packages
Signal chains are often used in signal processing applications to Analog Devices separately offers middleware add-ins such as gather and process data or to apply system controls based on real time operating systems, file systems, USB stacks, and analysis of real-time phenomena. TCP/IP stacks. For more information, see the following web Analog Devices eases signal processing system development by pages: providing signal processing components that are designed to • www.analog.com/ucos3 work together well. A tool for viewing relationships between specific applications and related components is available on the • www.analog.com/ucfs www.analog.com website. • www.analog.com/ucusbd The application signal chains page in the Circuits from the Lab® • www.analog.com/lwip site (http:\\www.analog.com\circuits) provides:
Algorithmic Modules
• Graphical circuit block diagram presentation of signal chains for a variety of circuit types and applications To speed development, Analog Devices offers add-ins that per- • Drill down links for components in each chain to selection form popular audio and video processing algorithms. These are guides and application information available for use with CrossCore Embedded Studio. For more information, visit www.analog.com and search on “Blackfin • Reference designs applying best practice design techniques software modules” or “SHARC software modules”. Rev. D | Page 16 of 114 | February 2019 Document Outline Blackfin+ Core Embedded Processor Features Peripherals Features Memory Table of Contents Revision History General Description Blackfin+ Processor Core Instruction Set Description Processor Infrastructure DMA Controllers Event Handling Trigger Routing Unit (TRU) General-Purpose I/O (GPIO) Pin Interrupts Pin Multiplexing Memory Architecture Internal (Core-Accessible) Memory OTP Memory Static Memory Controller (SMC) Dynamic Memory Controller (DMC) I/O Memory Space Booting Security Features Security Features Disclaimer Processor Safety Features Multi-Parity-Bit-Protected L1 Memories ECC-Protected L2 Memories CRC-Protected Memories Memory Protection System Protection Watchpoint Protection Watchdog Bandwidth Monitor Signal Watchdogs Up/Down Count Mismatch Detection Fault Management Additional Processor Peripherals Timers Serial Ports (SPORTs) General-Purpose Counters Parallel Peripheral Interface (PPI) Serial Peripheral Interface (SPI) Ports SPI Host Port (SPIHP) UART Ports 2-Wire Controller Interface (TWI) Mobile Storage Interface (MSI) Controller Area Network (CAN) USB 2.0 On-the-Go Dual-Role Device Controller Housekeeping ADC (HADC) System Crossbars (SCB) Power and Clock Management System Crystal Oscillator and USB Crystal Oscillator Real-Time Clock Clock Generation Clock Out/External Clock Power Management Reset Control Unit Voltage Regulation System Debug System Watchpoint Unit Debug Access Port Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits ADSP-BF706 EZ-KIT Mini Blackfin Low Power Imaging Platform (BLIP) Software Add-Ins for CrossCore Embedded Studio Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains ADSP-BF70x Detailed Signal Descriptions 184-Ball CSP_BGA Signal Descriptions GPIO Multiplexing for 184-Ball CSP_BGA 12 mm × 12 mm 88-Lead LFCSP (QFN) Signal Descriptions GPIO Multiplexing for 12 mm × 12 mm 88-Lead LFCSP (QFN) ADSP-BF70x Designer Quick Reference Specifications Operating Conditions Clock Related Operating Conditions Electrical Characteristics Total Internal Power Dissipation HADC HADC Electrical Characteristics HADC DC Accuracy HADC Timing Specifications Absolute Maximum Ratings ESD Sensitivity Timing Specifications Clock and Reset Timing Power-Up Reset Timing Asynchronous Read SMC Read Cycle Timing With Reference to SYS_CLKOUT Asynchronous Flash Read Asynchronous Page Mode Read Asynchronous Write SMC Write Cycle Timing With Reference to SYS_CLKOUT Asynchronous Flash Write All Accesses DDR2 SDRAM Clock and Control Cycle Timing DDR2 SDRAM Read Cycle Timing DDR2 SDRAM Write Cycle Timing Mobile DDR SDRAM Clock and Control Cycle Timing Mobile DDR SDRAM Read Cycle Timing Mobile DDR SDRAM Write Cycle Timing General-Purpose I/O Port Timing (GPIO) Timer Cycle Timing Up/Down Counter/Rotary Encoder Timing Debug Interface (JTAG Emulation Port) Timing Serial Ports Serial Peripheral Interface (SPI) Port—Master Timing Serial Peripheral Interface (SPI) Port—Slave Timing Serial Peripheral Interface (SPI) Port—SPI_RDY Slave Timing Serial Peripheral Interface (SPI) Port—Open Drain Mode (ODM) Timing Serial Peripheral Interface (SPI) Port—SPI_RDY Timing Enhanced Parallel Peripheral Interface Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing Controller Area Network (CAN) Interface Universal Serial Bus (USB) Mobile Storage Interface (MSI) Controller Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Capacitive Loading Environmental Conditions ADSP-BF70x 184-Ball CSP_BGA Ball Assignments (Numerical by Ball Number) ADSP-BF70x 12 mm × 12 mm 88-Lead LFCSP (QFN) Lead Assignments (Numerical by Lead Number) Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide