Datasheet ADSP-BF700, 701, 702, 703, 704, 705, 706, 707 (Analog Devices) - 17

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ADSP-BF700/701/702/703/704/705/706/707 ADSP-BF70x DETAILED SIGNAL DESCRIPTIONS
Table 6 provides a detailed description of each pin.
Table 6. ADSP-BF70x Detailed Signal Descriptions Port Name Direction Description
CAN_RX Input
Receive.
Typically an external CAN transceiver’s RX output. CAN_TX Output
Transmit.
Typically an external CAN transceiver’s TX input. CNT_DG Input
Count Down and Gate.
Depending on the mode of operation this input acts either as a count down signal or a gate signal Count Down - This input causes the GP counter to decrement Gate - Stops the GP counter from incrementing or decrementing. CNT_UD Input
Count Up and Direction.
Depending on the mode of operation this input acts either as a count up signal or a direction signal Count Up - This input causes the GP counter to increment Direction - Selects whether the GP counter is incrementing or decrementing. CNT_ZM Input
Count Zero Marker.
Input that connects to the zero marker output of a rotary device or detects the pressing of a pushbutton. DMC_Ann Output
Address n.
Address bus. DMC_BAn Output
Bank Address Input n.
Defines which internal bank an ACTIVATE, READ, WRITE, or PRECHARGE command is being applied to on the dynamic memory. Also defines which mode registers (MR, EMR, EMR2, and/or EMR3) are loaded during the LOAD MODE REGISTER command. DMC_CAS Output
Column Address Strobe.
Defines the operation for external dynamic memory to perform in conjunction with other DMC command signals. Connect to the CAS input of dynamic memory. DMC_CK Output
Clock.
Outputs DCLK to external dynamic memory. DMC_CK Output
Clock (Complement).
Complement of DMC_CK. DMC_CKE Output
Clock enable.
Active high clock enables. Connects to the dynamic memory’s CKE input. DMC_CSn Output
Chip Select n.
Commands are recognized by the memory only when this signal is asserted. DMC_DQnn I/O
Data n.
Bidirectional Data bus. DMC_LDM Output
Data Mask for Lower Byte.
Mask for DMC_DQ07:DMC_DQ00 write data when driven high. Sampled on both edges of the data strobe by the dynamic memory. DMC_LDQS I/O
Data Strobe for Lower Byte.
DMC_DQ07:DMC_DQ00 data strobe. Output with Write Data. Input with Read Data. May be single-ended or differential depending on register settings. DMC_LDQS I/O
Data Strobe for Lower Byte (complement).
Complement of LDQS. Not used in single-ended mode. DMC_ODT Output
On-die termination.
Enables dynamic memory termination resistances when driven high (assuming the memory is properly configured). ODT is enabled/disabled regardless of read or write commands. DMC_RAS Output
Row Address Strobe.
Defines the operation for external dynamic memory to perform in conjunction with other DMC command signals. Connect to the RAS input of dynamic memory. DMC_UDM Output
Data Mask for Upper Byte.
Mask for DMC_DQ15:DMC_DQ08 write data when driven high. Sampled on both edges of the data strobe by the dynamic memory. DMC_UDQS I/O
Data Strobe for Upper Byte.
DMC_DQ15:DMC_DQ08 data strobe. Output with Write Data. Input with Read Data. May be single-ended or differential depending on register settings. DMC_UDQS I/O
Data Strobe for Upper Byte (complement).
Complement of DMC_UDQS. Not used in single-ended mode. DMC_VREF Input
Voltage Reference.
Connect to half of the VDD_DMC voltage. Applies to the DMC0_VREF pin. DMC_WE Output
Write Enable.
Defines the operation for external dynamic memory to perform in conjunction with other DMC command signals. Connect to the WE input of dynamic memory. PPI_CLK I/O
Clock.
Input in external clock mode, output in internal clock mode. PPI_Dnn I/O
Data n.
Bidirectional data bus. PPI_FS1 I/O
Frame Sync 1 (HSYNC).
Behavior depends on EPPI mode. See the EPPI HRM chapter for more details. PPI_FS2 I/O
Frame Sync 2 (VSYNC).
Behavior depends on EPPI mode. See the EPPI HRM chapter for more details. PPI_FS3 I/O
Frame Sync 3 (FIELD).
Behavior depends on EPPI mode. See the EPPI HRM chapter for more details. HADC_VINn Input
Analog Input at channel n.
Analog voltage inputs for digital conversion. Rev. D | Page 17 of 114 | February 2019 Document Outline Blackfin+ Core Embedded Processor Features Peripherals Features Memory Table of Contents Revision History General Description Blackfin+ Processor Core Instruction Set Description Processor Infrastructure DMA Controllers Event Handling Trigger Routing Unit (TRU) General-Purpose I/O (GPIO) Pin Interrupts Pin Multiplexing Memory Architecture Internal (Core-Accessible) Memory OTP Memory Static Memory Controller (SMC) Dynamic Memory Controller (DMC) I/O Memory Space Booting Security Features Security Features Disclaimer Processor Safety Features Multi-Parity-Bit-Protected L1 Memories ECC-Protected L2 Memories CRC-Protected Memories Memory Protection System Protection Watchpoint Protection Watchdog Bandwidth Monitor Signal Watchdogs Up/Down Count Mismatch Detection Fault Management Additional Processor Peripherals Timers Serial Ports (SPORTs) General-Purpose Counters Parallel Peripheral Interface (PPI) Serial Peripheral Interface (SPI) Ports SPI Host Port (SPIHP) UART Ports 2-Wire Controller Interface (TWI) Mobile Storage Interface (MSI) Controller Area Network (CAN) USB 2.0 On-the-Go Dual-Role Device Controller Housekeeping ADC (HADC) System Crossbars (SCB) Power and Clock Management System Crystal Oscillator and USB Crystal Oscillator Real-Time Clock Clock Generation Clock Out/External Clock Power Management Reset Control Unit Voltage Regulation System Debug System Watchpoint Unit Debug Access Port Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits ADSP-BF706 EZ-KIT Mini Blackfin Low Power Imaging Platform (BLIP) Software Add-Ins for CrossCore Embedded Studio Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains ADSP-BF70x Detailed Signal Descriptions 184-Ball CSP_BGA Signal Descriptions GPIO Multiplexing for 184-Ball CSP_BGA 12 mm × 12 mm 88-Lead LFCSP (QFN) Signal Descriptions GPIO Multiplexing for 12 mm × 12 mm 88-Lead LFCSP (QFN) ADSP-BF70x Designer Quick Reference Specifications Operating Conditions Clock Related Operating Conditions Electrical Characteristics Total Internal Power Dissipation HADC HADC Electrical Characteristics HADC DC Accuracy HADC Timing Specifications Absolute Maximum Ratings ESD Sensitivity Timing Specifications Clock and Reset Timing Power-Up Reset Timing Asynchronous Read SMC Read Cycle Timing With Reference to SYS_CLKOUT Asynchronous Flash Read Asynchronous Page Mode Read Asynchronous Write SMC Write Cycle Timing With Reference to SYS_CLKOUT Asynchronous Flash Write All Accesses DDR2 SDRAM Clock and Control Cycle Timing DDR2 SDRAM Read Cycle Timing DDR2 SDRAM Write Cycle Timing Mobile DDR SDRAM Clock and Control Cycle Timing Mobile DDR SDRAM Read Cycle Timing Mobile DDR SDRAM Write Cycle Timing General-Purpose I/O Port Timing (GPIO) Timer Cycle Timing Up/Down Counter/Rotary Encoder Timing Debug Interface (JTAG Emulation Port) Timing Serial Ports Serial Peripheral Interface (SPI) Port—Master Timing Serial Peripheral Interface (SPI) Port—Slave Timing Serial Peripheral Interface (SPI) Port—SPI_RDY Slave Timing Serial Peripheral Interface (SPI) Port—Open Drain Mode (ODM) Timing Serial Peripheral Interface (SPI) Port—SPI_RDY Timing Enhanced Parallel Peripheral Interface Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing Controller Area Network (CAN) Interface Universal Serial Bus (USB) Mobile Storage Interface (MSI) Controller Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Capacitive Loading Environmental Conditions ADSP-BF70x 184-Ball CSP_BGA Ball Assignments (Numerical by Ball Number) ADSP-BF70x 12 mm × 12 mm 88-Lead LFCSP (QFN) Lead Assignments (Numerical by Lead Number) Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide