Datasheet ADSP-BF700, 701, 702, 703, 704, 705, 706, 707 (Analog Devices) - 90

ADSP-BF700/701/702/703/704/705/706/707 Serial Peripheral Interface (SPI) Port—SPI_RDY Timing
SPI_RDY is used to provide flow control. The CPOL and CPHA bits are set in SPI_CTL, while LEADX, LAGX, and STOP are in  SPI_DLY.
Table 58. SPI Port—SPI_RDY Timing VDD_EXT 1.8 V/3.3 V Nominal Parameter Min Max Unit
Timing Requirements tSRDYSCKM0 Minimum Setup Time for SPI_RDY De-assertion in (2.5 + 1.5 × BAUD1) × tSCLK0 + 14.5 ns Master Mode Before Last SPI_CLK Edge of Valid Data Transfer to Block Subsequent Transfer with CPHA = 0 tSRDYSCKM1 Minimum Setup Time for SPI_RDY De-assertion in (2.5 + BAUD1) × tSCLK0 + 14.5 ns Master Mode Before Last SPI_CLK Edge of Valid Data Transfer to Block Subsequent Transfer with CPHA = 1 Switching Characteristic tSRDYSCKM Time Between Assertion of SPI_RDY by Slave and 3 × tSCLK0 4 × tSCLK0 + 17.5 ns First Edge of SPI_CLK for New SPI Transfer with CPHA = 0 and BAUD = 0 (STOP, LEADX, LAGX = 0) Time Between Assertion of SPI_RDY by Slave and (4 + 1.5 × BAUD1) × tSCLK0 (5 + 1.5 × BAUD1) × tSCLK0 + 17.5 ns First Edge of SPI_CLK for New SPI Transfer with CPHA = 0 and BAUD ≥ 1 (STOP, LEADX, LAGX = 0) Time Between Assertion of SPI_RDY by Slave and (3 + 0.5 × BAUD1) × tSCLK0 (4 + 0.5 × BAUD1) × tSCLK0 + 17.5 ns First Edge of SPI_CLK for New SPI Transfer with CPHA = 1 (STOP, LEADX, LAGX = 0) 1 BAUD value set using the SPI_CLK.BAUD bits.
tSRDYSCKM0 SPI_RDY SPI_CLK (CPOL = 0) SPI_CLK (CPOL = 1)
Figure 36. SPI_RDY Setup Before SPI_CLK with CPHA = 0 Rev. D | Page 90 of 114 | February 2019 Document Outline Blackfin+ Core Embedded Processor Features Peripherals Features Memory Table of Contents Revision History General Description Blackfin+ Processor Core Instruction Set Description Processor Infrastructure DMA Controllers Event Handling Trigger Routing Unit (TRU) General-Purpose I/O (GPIO) Pin Interrupts Pin Multiplexing Memory Architecture Internal (Core-Accessible) Memory OTP Memory Static Memory Controller (SMC) Dynamic Memory Controller (DMC) I/O Memory Space Booting Security Features Security Features Disclaimer Processor Safety Features Multi-Parity-Bit-Protected L1 Memories ECC-Protected L2 Memories CRC-Protected Memories Memory Protection System Protection Watchpoint Protection Watchdog Bandwidth Monitor Signal Watchdogs Up/Down Count Mismatch Detection Fault Management Additional Processor Peripherals Timers Serial Ports (SPORTs) General-Purpose Counters Parallel Peripheral Interface (PPI) Serial Peripheral Interface (SPI) Ports SPI Host Port (SPIHP) UART Ports 2-Wire Controller Interface (TWI) Mobile Storage Interface (MSI) Controller Area Network (CAN) USB 2.0 On-the-Go Dual-Role Device Controller Housekeeping ADC (HADC) System Crossbars (SCB) Power and Clock Management System Crystal Oscillator and USB Crystal Oscillator Real-Time Clock Clock Generation Clock Out/External Clock Power Management Reset Control Unit Voltage Regulation System Debug System Watchpoint Unit Debug Access Port Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits ADSP-BF706 EZ-KIT Mini Blackfin Low Power Imaging Platform (BLIP) Software Add-Ins for CrossCore Embedded Studio Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains ADSP-BF70x Detailed Signal Descriptions 184-Ball CSP_BGA Signal Descriptions GPIO Multiplexing for 184-Ball CSP_BGA 12 mm × 12 mm 88-Lead LFCSP (QFN) Signal Descriptions GPIO Multiplexing for 12 mm × 12 mm 88-Lead LFCSP (QFN) ADSP-BF70x Designer Quick Reference Specifications Operating Conditions Clock Related Operating Conditions Electrical Characteristics Total Internal Power Dissipation HADC HADC Electrical Characteristics HADC DC Accuracy HADC Timing Specifications Absolute Maximum Ratings ESD Sensitivity Timing Specifications Clock and Reset Timing Power-Up Reset Timing Asynchronous Read SMC Read Cycle Timing With Reference to SYS_CLKOUT Asynchronous Flash Read Asynchronous Page Mode Read Asynchronous Write SMC Write Cycle Timing With Reference to SYS_CLKOUT Asynchronous Flash Write All Accesses DDR2 SDRAM Clock and Control Cycle Timing DDR2 SDRAM Read Cycle Timing DDR2 SDRAM Write Cycle Timing Mobile DDR SDRAM Clock and Control Cycle Timing Mobile DDR SDRAM Read Cycle Timing Mobile DDR SDRAM Write Cycle Timing General-Purpose I/O Port Timing (GPIO) Timer Cycle Timing Up/Down Counter/Rotary Encoder Timing Debug Interface (JTAG Emulation Port) Timing Serial Ports Serial Peripheral Interface (SPI) Port—Master Timing Serial Peripheral Interface (SPI) Port—Slave Timing Serial Peripheral Interface (SPI) Port—SPI_RDY Slave Timing Serial Peripheral Interface (SPI) Port—Open Drain Mode (ODM) Timing Serial Peripheral Interface (SPI) Port—SPI_RDY Timing Enhanced Parallel Peripheral Interface Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing Controller Area Network (CAN) Interface Universal Serial Bus (USB) Mobile Storage Interface (MSI) Controller Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Capacitive Loading Environmental Conditions ADSP-BF70x 184-Ball CSP_BGA Ball Assignments (Numerical by Ball Number) ADSP-BF70x 12 mm × 12 mm 88-Lead LFCSP (QFN) Lead Assignments (Numerical by Lead Number) Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide