Datasheet ADSP-BF512, BF514, BF516, BF518 (Analog Devices) - 4

ADSP-BF512 /BF514 /BF516 /BF518 ADDRESS ARITHMETIC UNIT SP I3 L3 B3 M3 FP I2 L2 B2 M2 P5 I1 L1 B1 M1 DAG1 P4 I0 L0 B0 M0 P3 DAG0 P2 DA1 32 P1 DA0 32 P0 Y 32 32 PREG RAB MEMOR O T SD 32 LD1 32 ASTAT 32 LD0 32 32 SEQUENCER R7.H R7.L R6.H R6.L R5.H R5.L ALIGN 16 16 R4.H R4.L 8 8 8 8 R3.H R3.L DECODE R2.H R2.L R1.H R1.L BARREL R0.H R0.L SHIFTER 40 40 LOOP BUFFER 40 40 A0 A1 CONTROL UNIT 32 32 DATA ARITHMETIC UNIT
Figure 2. Blackfin Processor Core The 40-bit shifter can perform shifts and rotates and is used to memory holds instructions only. The two data memories hold support normalization, field extract, and field deposit data, and a dedicated scratchpad data memory stores stack and instructions. local variable information. The program sequencer controls the flow of instruction execu- In addition, multiple L1 memory blocks are provided, offering a tion, including instruction alignment and decoding. For configurable mix of SRAM and cache. The memory manage- program flow control, the sequencer supports PC relative and ment unit (MMU) provides memory protection for individual indirect conditional jumps (with static branch prediction), and tasks that may be operating on the core and can protect system subroutine calls. Hardware is provided to support zero-over- registers from unintended access. head looping. The architecture is fully interlocked, meaning that The architecture provides three modes of operation: user mode, the programmer need not manage the pipeline when executing supervisor mode, and emulation mode. User mode has instructions with data dependencies. restricted access to certain system resources, thus providing a The address arithmetic unit provides two addresses for simulta- protected software environment, while supervisor mode has neous dual fetches from memory. It contains a multiported unrestricted access to the system and core resources. register file consisting of four sets of 32-bit index, modify, The Blackfin processor instruction set has been optimized so length, and base registers (for circular buffering), and eight that 16-bit opcodes represent the most frequently used instruc- additional 32-bit pointer registers (for C-style indexed stack tions, resulting in excellent compiled code density. Complex manipulation). DSP instructions are encoded into 32-bit opcodes, representing Blackfin processors support a modified Harvard architecture in fully featured multifunction instructions. Blackfin processors combination with a hierarchical memory structure. Level 1 (L1) support a limited multi-issue capability, where a 32-bit memories are those that typically operate at the full processor instruction can be issued in parallel with two 16-bit instruc- speed with little or no latency. At the L1 level, the instruction tions, allowing the programmer to use many of the core resources in a single instruction cycle. Rev. E | Page 4 of 63 | June 2020 Document Outline Blackfin Embedded Processor Features Memory Peripherals Table of Contents Revision History General Description Portable Low Power Architecture System Integration Blackfin Processor Core Memory Architecture Internal (On-Chip) Memory External (Off-Chip) Memory One-Time Programmable Memory I/O Memory Space Booting from ROM Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) DMA Controllers Processor Peripherals Real-Time Clock Watchdog Timer Timers 3-Phase PWM General-Purpose (GP) Counter Serial Ports Serial Peripheral Interface (SPI) Ports UART Ports 2-Wire Interface (TWI) Removable Storage Interface (RSI) 10/100 Ethernet MAC IEEE 1588 Support Ports General-Purpose I/O (GPIO) Parallel Peripheral Interface (PPI) Code Security with Lockbox Secure Technology Lockbox Secure Technology Disclaimer Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Savings Voltage Regulation Interface Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Signal Descriptions Specifications Operating Conditions Clock Related Operating Conditions Electrical Characteristics Total Power Dissipation Absolute Maximum Ratings ESD Sensitivity Timing Specifications Clock and Reset Timing Asynchronous Memory Read Cycle Timing Asynchronous Memory Write Cycle Timing SDRAM Interface Timing External DMA Request Timing Parallel Peripheral Interface Timing RSI Controller Timing Serial Ports Serial Peripheral Interface (SPI) Port—Master Timing Serial Peripheral Interface (SPI) Port—Slave Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing General-Purpose Port Timing Timer Clock Timing Timer Cycle Timing Up/Down Counter/Rotary Encoder Timing 10/100 Ethernet MAC Controller Timing JTAG Test And Emulation Port Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Example System Hold Time Calculation Capacitive Loading Thermal Characteristics 176-Lead LQFP_EP Lead Assignment 168-Ball CSP_BGA Ball Assignment Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide