Datasheet GD32E507xx (GigaDevice) - 24

GD32E507xx Datasheet
Pin I/O Pin Name Pins Functions description(3) Type(1) Level(2)
Alternate1: CMP3_OUT Alternate2: EXMC_D9 Remap: TIMER0_CH2_ON Default: PE13 Alternate1: CMP1_OUT PE13 66 I/O 5VT Alternate2: EXMC_D10 Remap: TIMER0_CH2 Default: PE14 PE14 67 I/O 5VT Alternate2: EXMC_D11 Remap: TIMER0_CH3 Default: PE15 PE15 68 I/O 5VT Alternate2: EXMC_D12 Remap: TIMER0_BRKIN Default: PB10 Alternate1: CAN2_RX, USBHS_ULPI_D3, PB10 69 I/O 5VT SHRTIMER_FLT2 Alternate2: I2C1_SCL, USART2_TX, ETH_MII_RX_ER Remap: TIMER1_CH2 Default: PB11 Alternate1: CAN2_TX, USBHS_ULPI_D4, SHRTIMER_FLT3 PB11 70 I/O 5VT Alternate2: I2C1_SDA, USART2_RX, ETH_MII_TX_EN, ETH_RMII_TX_EN, CMP5_IP Remap: TIMER1_CH3 VSS_1 71 P Default: VSS_1 VDD_1 72 P Default: VDD_1 Default: PB12 Alternate1: USBHS_ULPI_D5, SHRTIMER_ST2CH0 PB12 73 I/O 5VT Alternate2: SPI1_NSS, I2S1_WS, I2C1_SMBA, USART2_CK, TIMER0_BRKIN, CAN1_RX, ETH_MII_TXD0, ETH_RMII_TXD0 Default: PB13 Alternate1: USBHS_ULPI_D6, SHRTIMER_ST2CH1 PB13 74 I/O 5VT Alternate2: SPI1_SCK, I2S1_CK, USART2_CTS, TIMER0_CH0_ON, CAN1_TX, ETH_MII_TXD1, ETH_RMII_TXD1, I2C1_TXFRAME Default: PB14 Alternate1: SHRTIMER_ST3CH0, I2S1_ADD_SD PB14 75 I/O 5VT Alternate2: SPI1_MISO, USART2_RTS, TIMER0_CH1_ON, TIMER11_CH0(4) Default: PB15 PB15 76 I/O 5VT Alternate1: SHRTIMER_ST3CH1 Alternate2: SPI1_MOSI, TIMER0_CH2_ON, I2S1_SD, 23 Document Outline Table of Contents List of Figures List of Tables 1. General description 2. Device overview 2.1. Device information 2.2. Block diagram 2.3. Pinouts and pin assignment 2.4. Memory map 2.5. Clock tree 2.6. Pin definitions 2.6.1. GD32E507Zx LQFP144 pin definitions 2.6.2. GD32E507Vx LQFP100 pin definitions 2.6.3. GD32E507Rx LQFP64 pin definitions 3. Functional description 3.1. Arm® Cortex®-M33 core 3.2. Embedded memory 3.3. Clock, reset and supply management 3.4. Boot modes 3.5. Power saving modes 3.6. Analog to digital converter (ADC) 3.7. Digital to analog converter (DAC) 3.8. DMA 3.9. General-purpose inputs/outputs (GPIOs) 3.10. Timers and PWM generation 3.11. Real time clock (RTC) 3.12. Inter-integrated circuit (I2C) 3.13. Serial peripheral interface (SPI) 3.14. Universal synchronous asynchronous receiver transmitter (USART) 3.15. Inter-IC sound (I2S) 3.16. Universal serial bus High-Speed interface (USBHS) 3.17. Controller area network (CAN) 3.18. Ethernet (ENET) 3.19. External memory controller (EXMC) 3.20. Comparators (CMP) 3.21. Trigonometric Math Unit (TMU) 3.22. Super High-Resolution Timer (SHRTIMER) 3.23. Serial/Quad Parallel Interface (SQPI) 3.24. Debug mode 3.25. Package and operation temperature 4. Electrical characteristics 4.1. Absolute maximum ratings 4.2. Operating conditions characteristics 4.3. Power consumption 4.4. EMC characteristics 4.5. Power supply supervisor characteristics 4.6. Electrical sensitivity 4.7. External clock characteristics 4.8. Internal clock characteristics 4.9. PLL characteristics 4.10. Memory characteristics 4.11. NRST pin characteristics 4.12. GPIO characteristics 4.13. Temperature sensor characteristics 4.14. ADC characteristics 4.15. DAC characteristics 4.16. Comparators characteristics 4.17. Trigonometric Math Unit (TMU) characteristics 4.18. I2C characteristics 4.19. SPI characteristics 4.20. I2S characteristics 4.21. USART characteristics 4.22. CAN characteristics 4.23. USBHS characteristics 4.24. EXMC characteristics 4.25. Serial/Quad Parallel Interface (SQPI) characteristics 4.26. Super High-Resolution Timer (SHRTIMER) characteristics 4.27. TIMER characteristics 4.28. WDGT characteristics 4.29. Parameter condition 5. Package information 5.1. LQFP144 package outline dimensions 5.2. LQFP100 package outline dimensions 5.3. LQFP64 package outline dimensions 6. Ordering information 7. Revision history