Datasheet GD32E507xx (GigaDevice) - 31

GD32E507xx Datasheet
Pin I/O Pin Name Pins Functions description(3) Type(1) Level(2)
Alternate2: ADC01_IN13, ETH_MII_TX_CLK VSSA 19 P Default: VSSA VREF- 20 P Default: VREF- VREF+ 21 P Default: VREF+ VDDA 22 P Default: VDDA Default: PA0 Alternate2: WKUP0, USART1_CTS, ADC01_IN0, PA0-WKUP0 23 I/O TIMER1_CH0, TIMER1_ETI, TIMER4_CH0, TIMER7_ETI(4), ETH_MII_CRS Default: PA1 PA1 24 I/O Alternate2: USART1_RTS, ADC01_IN1, TIMER4_CH1, TIMER1_CH1, ETH_MII_RX_CLK, ETH_RMII_REF_CLK Default: PA2 Alternate1: CMP1_OUT PA2 25 I/O Alternate2: USART1_TX, TIMER4_CH2, ADC01_IN2, TIMER8_CH0(4), TIMER1_CH2, ETH_MII_MDIO, ETH_RMII_MDIO, SPI0_IO2, WKUP3, CMP1_IM6 Default: PA3 Alternate1: USBHS_ULPI_D0 PA3 26 I/O Alternate2: USART1_RX, TIMER4_CH3, ADC01_IN3, TIMER1_CH3, TIMER8_CH1(4), ETH_MII_COL, SPI0_IO3 VSS_4 27 P Default: VSS_4 VDD_4 28 P Default: VDD_4 Default: PA4 Alternate2: SPI0_NSS, USART1_CK, DAC_OUT0, PA4 29 I/O ADC01_IN4, CMP1_IM4, CMP3_IM4, CMP5_IM4 Remap: SPI2_NSS, I2S2_WS Default: PA5 Alternate1: USBHS_ULPI_CK PA5 30 I/O Alternate2: SPI0_SCK, ADC01_IN5, DAC_OUT1, CMP1_IM5, CMP3_IM5, CMP5_IM5 Default: PA6 Alternate2: SPI0_MISO, TIMER7_BRKIN(4), ADC01_IN6, PA6 31 I/O TIMER2_CH0, TIMER12_CH0(4) Remap: TIMER0_BRKIN Default: PA7 Alternate2: SPI0_MOSI, TIMER7_CH0_ON(4), PA7 32 I/O ADC01_IN7, TIMER2_CH1, TIMER13_CH0(4), ETH_MII_RX_DV, ETH_RMII_CRS_DV, CMP1_IP Remap: TIMER0_CH0_ON PC4 33 I/O Default: PC4 30 Document Outline Table of Contents List of Figures List of Tables 1. General description 2. Device overview 2.1. Device information 2.2. Block diagram 2.3. Pinouts and pin assignment 2.4. Memory map 2.5. Clock tree 2.6. Pin definitions 2.6.1. GD32E507Zx LQFP144 pin definitions 2.6.2. GD32E507Vx LQFP100 pin definitions 2.6.3. GD32E507Rx LQFP64 pin definitions 3. Functional description 3.1. Arm® Cortex®-M33 core 3.2. Embedded memory 3.3. Clock, reset and supply management 3.4. Boot modes 3.5. Power saving modes 3.6. Analog to digital converter (ADC) 3.7. Digital to analog converter (DAC) 3.8. DMA 3.9. General-purpose inputs/outputs (GPIOs) 3.10. Timers and PWM generation 3.11. Real time clock (RTC) 3.12. Inter-integrated circuit (I2C) 3.13. Serial peripheral interface (SPI) 3.14. Universal synchronous asynchronous receiver transmitter (USART) 3.15. Inter-IC sound (I2S) 3.16. Universal serial bus High-Speed interface (USBHS) 3.17. Controller area network (CAN) 3.18. Ethernet (ENET) 3.19. External memory controller (EXMC) 3.20. Comparators (CMP) 3.21. Trigonometric Math Unit (TMU) 3.22. Super High-Resolution Timer (SHRTIMER) 3.23. Serial/Quad Parallel Interface (SQPI) 3.24. Debug mode 3.25. Package and operation temperature 4. Electrical characteristics 4.1. Absolute maximum ratings 4.2. Operating conditions characteristics 4.3. Power consumption 4.4. EMC characteristics 4.5. Power supply supervisor characteristics 4.6. Electrical sensitivity 4.7. External clock characteristics 4.8. Internal clock characteristics 4.9. PLL characteristics 4.10. Memory characteristics 4.11. NRST pin characteristics 4.12. GPIO characteristics 4.13. Temperature sensor characteristics 4.14. ADC characteristics 4.15. DAC characteristics 4.16. Comparators characteristics 4.17. Trigonometric Math Unit (TMU) characteristics 4.18. I2C characteristics 4.19. SPI characteristics 4.20. I2S characteristics 4.21. USART characteristics 4.22. CAN characteristics 4.23. USBHS characteristics 4.24. EXMC characteristics 4.25. Serial/Quad Parallel Interface (SQPI) characteristics 4.26. Super High-Resolution Timer (SHRTIMER) characteristics 4.27. TIMER characteristics 4.28. WDGT characteristics 4.29. Parameter condition 5. Package information 5.1. LQFP144 package outline dimensions 5.2. LQFP100 package outline dimensions 5.3. LQFP64 package outline dimensions 6. Ordering information 7. Revision history