Datasheet ALT80800 (Allegro) - 3
| Manufacturer | Allegro |
| Description | Automotive-Grade, Constant-Current 2.0 A PWM Dimmable Synchronous Buck LED Driver |
| Pages / Page | 23 / 3 — Automotive-Grade, Constant-Current 2.0 A. ALT80800. PWM Dimmable … |
| File Format / Size | PDF / 2.2 Mb |
| Document Language | English |
Automotive-Grade, Constant-Current 2.0 A. ALT80800. PWM Dimmable Synchronous Buck LED Driver
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Automotive-Grade, Constant-Current 2.0 A ALT80800 PWM Dimmable Synchronous Buck LED Driver PINOUT DIAGRAM AND TERMINAL LIST TABLE TSSOP-16 (LP) Pinout Diagram Terminal List Table Number Name Function
PGND 1 16 SW 1, 2 PGND Power ground terminal. PGND 2 15 BOOT 3 VIN Supply input voltage for power stage. VIN 3 14 VCCIN 4 EN Enable pin for internal LDO regulator and whole IC. EN pin can EN 4 13 FFn also be used as PWM dimming when keeping PWM pin High. PAD PWM 5 12 VCC 5 PWM Logic input for PWM dimming: when PWM = LOW, LED is off; if PWM = High and at the same time EN is enabled, LED is ON. FDSET 6 11 SGND ADIM 7 10 CSL FDSET pin to set the LED Open fault mask threshold. Connect to a voltage divider formed between VIN and PGND. When VIN TON 8 9 CSH 6 FDSET is low, resulting in FDSET below the internal reference, LED Open Fault detection will be masked. Analog dimming control voltage input. If not used for analog 7 ADIM dimming, tie ADIM to 5 V or VCC; if used for analog dimming, keep ADIM less than 2.5 V. 8 TON Regulator on-time setting resistor terminal. Connect a resistor between TON pin and SGND to set the switching frequency. 9 CSH Current Sense (positive end) feedback input for LED current. 10 CSL Current Sense (negative end) feedback input for LED current. 11 SGND Signal ground terminal. 12 VCC Internal IC bias regulator output. Connect at least 1 µF MLCC to PGND. Can be used to supply up to 14 mA for external load. 13 FFn Open-drain output which is pulled low in case of fault. Connect through an external pull-up resistor to the desired logic level. 14 VCCIN It is recommended to connect VCCIN to VIN to bias the internal LDO regulator. 15 BOOT High-side gate driver bootstrap terminal; a 0.47uF capacitor is recommended between BOOT and SW. 16 SW Switched output terminal. The output inductor should be connected to this pin. – PAD Exposed pad for enhanced thermal dissipation; connect to ground. 3 Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com Document Outline Features and Benefits Description Applications Package Typical Application Circuit Selection Guide Specifications Absolute Maximum Ratings Thermal Characteristics Pinout Diagrams and Terminal List Tables Functional Block Diagrams Electrical Characteristics Functional Description Application Circuit Diagrams
PGND 1 16 SW 1, 2 PGND Power ground terminal. PGND 2 15 BOOT 3 VIN Supply input voltage for power stage. VIN 3 14 VCCIN 4 EN Enable pin for internal LDO regulator and whole IC. EN pin can EN 4 13 FFn also be used as PWM dimming when keeping PWM pin High. PAD PWM 5 12 VCC 5 PWM Logic input for PWM dimming: when PWM = LOW, LED is off; if PWM = High and at the same time EN is enabled, LED is ON. FDSET 6 11 SGND ADIM 7 10 CSL FDSET pin to set the LED Open fault mask threshold. Connect to a voltage divider formed between VIN and PGND. When VIN TON 8 9 CSH 6 FDSET is low, resulting in FDSET below the internal reference, LED Open Fault detection will be masked. Analog dimming control voltage input. If not used for analog 7 ADIM dimming, tie ADIM to 5 V or VCC; if used for analog dimming, keep ADIM less than 2.5 V. 8 TON Regulator on-time setting resistor terminal. Connect a resistor between TON pin and SGND to set the switching frequency. 9 CSH Current Sense (positive end) feedback input for LED current. 10 CSL Current Sense (negative end) feedback input for LED current. 11 SGND Signal ground terminal. 12 VCC Internal IC bias regulator output. Connect at least 1 µF MLCC to PGND. Can be used to supply up to 14 mA for external load. 13 FFn Open-drain output which is pulled low in case of fault. Connect through an external pull-up resistor to the desired logic level. 14 VCCIN It is recommended to connect VCCIN to VIN to bias the internal LDO regulator. 15 BOOT High-side gate driver bootstrap terminal; a 0.47uF capacitor is recommended between BOOT and SW. 16 SW Switched output terminal. The output inductor should be connected to this pin. – PAD Exposed pad for enhanced thermal dissipation; connect to ground. 3 Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com Document Outline Features and Benefits Description Applications Package Typical Application Circuit Selection Guide Specifications Absolute Maximum Ratings Thermal Characteristics Pinout Diagrams and Terminal List Tables Functional Block Diagrams Electrical Characteristics Functional Description Application Circuit Diagrams
