Datasheet ADG858 (Analog Devices) - 10
| Manufacturer | Analog Devices |
| Description | 0.58 Ω CMOS, 1.8 V to 5.5 V, Quad SPDT/2:1 Mux in Mini LFCSP |
| Pages / Page | 16 / 10 — ADG858. Data Sheet. TEST CIRCUITS. IDS. RON = V1/IDS. IS (OFF). ID (OFF). … |
| Revision | B |
| File Format / Size | PDF / 305 Kb |
| Document Language | English |
ADG858. Data Sheet. TEST CIRCUITS. IDS. RON = V1/IDS. IS (OFF). ID (OFF). ID (ON). VDD. 0.1µF. S1B. 50%. S1A. OUT. VIN. 50Ω. 35pF. 90%. VOUT. GND. tOFF. 80%. tBBM
Model Line for this Datasheet
Text Version of Document
ADG858 Data Sheet TEST CIRCUITS IDS V1 S D VS RON = V1/IDS
19 0 0- 709 0 Figure 16. On Resistance
IS (OFF) ID (OFF) S D A A VS VD
020 090- 07 Figure 17. Off Leakage
ID (ON) S D NC A
1
V
02
D
0- 0709 Figure 18. On Leakage
VDD 0.1µF VDD V S1B S V 50% 50% S1A D OUT VIN RL CL IN 50Ω 35pF 90% 90% VOUT GND
022
t
0-
ON tOFF
09 07 Figure 19. Switching Times, tON, tOFF
VDD 0.1µF 50% 50% V 0V DD VIN V S1B S V V OUT OUT S1A D 80% 80% RL CL IN 50Ω 35pF tBBM tBBM GND
023 0- 0709 Figure 20. Break-Before-Make Time Delay, tBBM
VDD SW ON SW OFF VIN S1B NC D VS S1A VOUT IN 1nF VOUT ∆VOUT GND QINJ = CL × ∆VOUT
4 02 0- 09 07 Figure 21. Charge Injection Rev. B | Page 10 of 16 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS REVISTION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TEST CIRCUITS TERMINOLOGY OUTLINE DIMENSIONS ORDERING GUIDE
19 0 0- 709 0 Figure 16. On Resistance
IS (OFF) ID (OFF) S D A A VS VD
020 090- 07 Figure 17. Off Leakage
ID (ON) S D NC A
1
V
02
D
0- 0709 Figure 18. On Leakage
VDD 0.1µF VDD V S1B S V 50% 50% S1A D OUT VIN RL CL IN 50Ω 35pF 90% 90% VOUT GND
022
t
0-
ON tOFF
09 07 Figure 19. Switching Times, tON, tOFF
VDD 0.1µF 50% 50% V 0V DD VIN V S1B S V V OUT OUT S1A D 80% 80% RL CL IN 50Ω 35pF tBBM tBBM GND
023 0- 0709 Figure 20. Break-Before-Make Time Delay, tBBM
VDD SW ON SW OFF VIN S1B NC D VS S1A VOUT IN 1nF VOUT ∆VOUT GND QINJ = CL × ∆VOUT
4 02 0- 09 07 Figure 21. Charge Injection Rev. B | Page 10 of 16 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS REVISTION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TEST CIRCUITS TERMINOLOGY OUTLINE DIMENSIONS ORDERING GUIDE
