Datasheet SiT1881 (SiTime) - 7
| Manufacturer | SiTime |
| Description | Automotive Ultra-Low Power, Low Jitter 32.768 kHz Oscillator |
| Pages / Page | 8 / 7 — SiT1881. Layout Guidelines. Manufacturing Guidelines. Figure 3. SiT1881 … |
| File Format / Size | PDF / 472 Kb |
| Document Language | English |
SiT1881. Layout Guidelines. Manufacturing Guidelines. Figure 3. SiT1881 Layout Example
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PRELIMINARY
SiT1881
Automotive Ultra-Low Power, Low Jitter 32.768 kHz Oscillator
Layout Guidelines Manufacturing Guidelines
Sample PCB layout is shown in the following figure. It is The SiT1881 is a precision timing device. Proper PCB strongly recommended that the PCB designer observe the solder and cleaning processes must be followed to ensure following layout guidelines: best performance and long-term reliability. ◼ Do not connect any of the pads directly to a copper ◼ For additional manufacturing guidelines and marking/ polygon or a wide PCB trace. This may cause bad tape-reel instructions, refer to SiTime Manufacturing solder joints due to non-uniform heating transfer Notes. during the assembly process ◼ Provide short length (>0.5 mm) and thin width (≤0.25 mm) traces to each pad and then to the respective copper polygon or wide trace ◼ Keep mirror symmetry of the traces X-Y planes. This will prevent the rotation effect during reflow ◼ Keep high-current and high-speed traces away from the oscillator o Route high edge-rate and noisy signals at least 1 mm away from clock-out and pin1 signal traces o The use of orthogonal routes is recommended to avoid signal coupling
Figure 3. SiT1881 Layout Example
It is recommended to connect VDD and GND pins with polygons or thick wires to corresponding layers of the board. For GND connection it would apply for both device and bypass connections. ◼ For additional layout recommendations, refer to the Best Design Layout Practices. Rev 0.8 Page 7 of 8 Proprietary & Confidential of SiTime
SiT1881
Automotive Ultra-Low Power, Low Jitter 32.768 kHz Oscillator
Layout Guidelines Manufacturing Guidelines
Sample PCB layout is shown in the following figure. It is The SiT1881 is a precision timing device. Proper PCB strongly recommended that the PCB designer observe the solder and cleaning processes must be followed to ensure following layout guidelines: best performance and long-term reliability. ◼ Do not connect any of the pads directly to a copper ◼ For additional manufacturing guidelines and marking/ polygon or a wide PCB trace. This may cause bad tape-reel instructions, refer to SiTime Manufacturing solder joints due to non-uniform heating transfer Notes. during the assembly process ◼ Provide short length (>0.5 mm) and thin width (≤0.25 mm) traces to each pad and then to the respective copper polygon or wide trace ◼ Keep mirror symmetry of the traces X-Y planes. This will prevent the rotation effect during reflow ◼ Keep high-current and high-speed traces away from the oscillator o Route high edge-rate and noisy signals at least 1 mm away from clock-out and pin1 signal traces o The use of orthogonal routes is recommended to avoid signal coupling
Figure 3. SiT1881 Layout Example
It is recommended to connect VDD and GND pins with polygons or thick wires to corresponding layers of the board. For GND connection it would apply for both device and bypass connections. ◼ For additional layout recommendations, refer to the Best Design Layout Practices. Rev 0.8 Page 7 of 8 Proprietary & Confidential of SiTime
