Datasheet VEML4031X00 (Vishay) - 4
| Manufacturer | Vishay |
| Description | High Accuracy Ambient Light Sensor With I 2C Interface |
| Pages / Page | 15 / 4 — VEML4031X00. PARAMETER TIMING INFORMATION |
| File Format / Size | PDF / 254 Kb |
| Document Language | English |
VEML4031X00. PARAMETER TIMING INFORMATION
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VEML4031X00
www.vishay.com Vishay Semiconductors
PARAMETER TIMING INFORMATION
I2C bus clock (SCLK) I2C bus data SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0
W
(SDAT) Start by ACK by ACK by master slave slave I2C bus slave address byte Command code I2C bus clock (SCLK) I2C bus data SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 (SDAT) ACK by Stop by slave master Data byte Fig. 3 - I2C Bus Timing for Sending Word Command Format I2C bus clock (SCLK) I2C bus data SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0
W
(SDAT) Start by ACK by ACK by master slave slave I2C bus slave address byte Command code I2C bus clock (SCLK) I2C bus data SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0
R
(SDAT) Start by ACK by NACK by Stop by master slave master master I2C bus slave address byte Data byte Fig. 4 - I2C Bus Timing for Receive Word Command Format Rev. 1.1, 12-Mar-2025
4
Document Number: 80348 For technical questions, contact: sensorstechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
www.vishay.com Vishay Semiconductors
PARAMETER TIMING INFORMATION
I2C bus clock (SCLK) I2C bus data SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0
W
(SDAT) Start by ACK by ACK by master slave slave I2C bus slave address byte Command code I2C bus clock (SCLK) I2C bus data SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 (SDAT) ACK by Stop by slave master Data byte Fig. 3 - I2C Bus Timing for Sending Word Command Format I2C bus clock (SCLK) I2C bus data SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0
W
(SDAT) Start by ACK by ACK by master slave slave I2C bus slave address byte Command code I2C bus clock (SCLK) I2C bus data SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0
R
(SDAT) Start by ACK by NACK by Stop by master slave master master I2C bus slave address byte Data byte Fig. 4 - I2C Bus Timing for Receive Word Command Format Rev. 1.1, 12-Mar-2025
4
Document Number: 80348 For technical questions, contact: sensorstechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
