Datasheet RA2L2 (Renesas) - 10

RA2L2 Datasheet 1. Overview 1.5 Pin Functions
Table 1.13 Pin functions (1 of 3) Function Signal I/O Description
Power supply VCC Input Power supply pin. Connect it to the system power supply. Connect this pin to VSS by a 0.1-µF capacitor. Place the capacitor close to the pin. VCL I/O Connect this pin to the VSS pin by the smoothing capacitor used to stabilize the internal power supply. Place the capacitor close to the pin. VSS Input Ground pin. Connect it to the system power supply (0 V). Clock XTAL Output Pins for a crystal resonator. An external clock signal can be input through the EXTAL pin. EXTAL Input XCIN Input Input/output pins for the sub-clock oscillator. Connect a crystal resonator between XCOUT and XCIN. XCOUT Output CLKOUT Output Clock output pin Operating mode control MD Input Pin for setting the operating mode. The signal level on this pin must not be changed during operation mode transition on release from the reset state. System control RES Input Reset signal input pin. The MCU enters the reset state when this signal goes low. CAC CACREF Input Measurement reference clock input pin On-chip debug SWDIO I/O Serial wire debug data input/output pin SWCLK Input Serial wire clock pin Interrupt NMI Input Non-maskable interrupt request pin IRQ0 to IRQ7 Input Maskable interrupt request pins GPT GTETRGA, GTETRGB Input External trigger input pins GTIOCnA (n = 0, 4 to 9), I/O Input capture, output compare, or PWM output pins GTIOCnB (n = 0, 4 to 9) GTIU Input Hall sensor input pin U GTIV Input Hall sensor input pin V GTIW Input Hall sensor input pin W GTOUUP Output 3-phase PWM output for BLDC motor control (positive U phase) GTOULO Output 3-phase PWM output for BLDC motor control (negative U phase) GTOVUP Output 3-phase PWM output for BLDC motor control (positive V phase) GTOVLO Output 3-phase PWM output for BLDC motor control (negative V phase) GTOWUP Output 3-phase PWM output for BLDC motor control (positive W phase) GTOWLO Output 3-phase PWM output for BLDC motor control (negative W phase) AGTW AGTEE0, AGTEE1 Input External event input enable signals AGTIO0, AGTIO1 I/O External event input and pulse output pins AGTO0, AGTO1 Output Pulse output pins AGTOA0, AGTOA1 Output Output compare match A output pins AGTOB0, AGTOB1 Output Output compare match B output pins RTC RTCOUT Output Output pin for 1-Hz or 64-Hz clock R01DS0445EJ0110 Rev.1.10 Page 10 of 108 Mar 12, 2025 Document Outline Features 1. Overview 1.1 Function Outline 1.2 Block Diagram 1.3 Part Numbering 1.4 Function Comparison 1.5 Pin Functions 1.6 Pin Assignments 1.7 Pin Lists 2. Electrical Characteristics 2.1 Absolute Maximum Ratings 2.2 DC Characteristics 2.2.1 Tj/Ta Definition 2.2.2 I/O VIH, VIL 2.2.3 I/O IOH, IOL 2.2.4 I/O VOH, VOL, and Other Characteristics 2.2.5 Operating and Standby Current 2.2.6 VCC Rise and Fall Gradient and Ripple Frequency 2.2.7 Thermal Characteristics 2.3 AC Characteristics 2.3.1 Frequency 2.3.2 Clock Timing 2.3.3 Reset Timing 2.3.4 Wakeup Time 2.3.5 NMI and IRQ Noise Filter 2.3.6 I/O Ports, POEG, GPT, AGTW, KINT, and ADC12 Trigger Timing 2.3.7 CAC Timing 2.3.8 SCI Timing 2.3.9 SPI Timing 2.3.10 I3C Timing 2.3.11 SSIE Timing 2.3.12 UARTA Timing 2.3.13 CLKOUT Timing 2.4 USB Characteristics 2.4.1 USBFS Timing 2.4.2 USBCC Characteristics 2.5 ADC12 Characteristics 2.6 TSN Characteristics 2.7 OSC Stop Detect Characteristics 2.8 POR and LVD Characteristics 2.9 Flash Memory Characteristics 2.9.1 Code Flash Memory Characteristics 2.9.2 Data Flash Memory Characteristics 2.10 Serial Wire Debug (SWD) Appendix 1. Port States in each Processing Mode Appendix 2. Package Dimensions Appendix 3. I/O Registers 3.1 Peripheral Base Addresses 3.2 Access Cycles Revision History General Precautions Notice