Datasheet Si5351 (Silicon Labs) - 9

ManufacturerSilicon Labs
DescriptionI2C-Programmable Any-Frequency CMOS Clock Generator + VCXO
Pages / Page41 / 9 — S i 5 3 5 1 A / B / C - B. Table 9. Thermal Characteristics. Parameter. …
File Format / SizePDF / 1.8 Mb
Document LanguageEnglish

S i 5 3 5 1 A / B / C - B. Table 9. Thermal Characteristics. Parameter. Symbol. Test Condition. Package. Value. Unit

S i 5 3 5 1 A / B / C - B Table 9 Thermal Characteristics Parameter Symbol Test Condition Package Value Unit

Model Line for this Datasheet

Si5351

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S i 5 3 5 1 A / B / C - B Table 9. Thermal Characteristics Parameter Symbol Test Condition Package Value Unit
Thermal Resistance 10-MSOP 131 °C/W  Junction to Ambient JA Still Air 20-QFN 119 °C/W Thermal Resistance  Junction to Case JC Still Air 20-QFN 16 °C/W
Table 10. Absolute Maximum Ratings1 Parameter Symbol Test Condition Value Unit
DC Supply Voltage VDD_max –0.5 to 3.8 V VIN_CLKIN CLKIN, SCL, SDA –0.5 to 3.8 V Input Voltage VIN_VC VC –0.5 to (VDD+0.3) V VIN_XA/B Pins XA, XB –0.5 to 1.3 V V Junction Temperature TJ –55 to 150 °C Soldering Temperature (Pb-free profile)2 TPEAK 260 °C Soldering Temperature Time at TPEAK (Pb-free profile)2 TP 20–40 Sec
Notes: 1.
Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
2.
The device is compliant with JEDEC J-STD-020.
Rev. 1.0 9
Document Outline 1. Electrical Specifications 2. Detailed Block Diagrams 3. Functional Description 3.1. Input Stage 3.1.1. Crystal Inputs (XA, XB) 3.1.2. External Clock Input (CLKIN) 3.1.3. Voltage Control Input (VC) 3.2. Synthesis Stages 3.3. Output Stage 3.4. Spread Spectrum 3.5. Control Pins (OEB, SSEN) 3.5.1. Output Enable (OEB) 3.5.2. Spread Spectrum Enable (SSEN)—Si5351A and Si5351B only 4. I2C Interface 5. Configuring the Si5351 5.1. Writing a Custom Configuration to RAM 5.2. Si5351 Application Examples 5.3. Replacing Crystals and Crystal Oscillators 5.4. Replacing Crystals, Crystal Oscillators, and VCXOs 5.5. Replacing Crystals, Crystal Oscillators, and PLLs 5.6. Applying a Reference Clock at XTAL Input 5.7. HCSL Compatible Outputs 6. Design Considerations 6.1. Power Supply Decoupling/Filtering 6.2. Power Supply Sequencing 6.3. External Crystal 6.4. External Crystal Load Capacitors 6.5. Unused Pins 6.6. Trace Characteristics 7. Register Map Summary 8. Register Descriptions 9. Si5351 Pin Descriptions 9.1. Si5351A 20-pin QFN 9.2. Si5351B 20-Pin QFN 9.3. Si5351C 20-Pin QFN 9.4. Si5351A 10-Pin MSOP 10. Ordering Information 11. Package Outlines 11.1. 20-pin QFN 12. Land Pattern: 20-Pin QFN 12.1. 10-Pin MSOP Package Outline 13. Land Pattern: 10-Pin MSOP 14. Top Marking 14.1. 20-Pin QFN Top Marking 14.2. Top Marking Explanation 14.3. 10-Pin MSOP Top Marking 14.4. Top Marking Explanation Document Change List