Register Description R820T2 (Rafael Micro) - 3
| Manufacturer | Rafael Micro |
| Description | High Performance Low Power Advanced Digital TV Silicon Tuner in QFN-24 package |
| Pages / Page | 11 / 3 — Write Mode |
| File Format / Size | PDF / 229 Kb |
| Document Language | English |
Write Mode
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Write Mode
When the slave address matches the I2C device ID with write control bit , I2C start interprets the following first byte as first written register address. These following bytes are all the register data (page write I2C control). Register 0 to Register 4 are reserved for internal use only and can be written by I2C write command. Figure 1-1 : The Typical Write Mode Sequence {Chip ID,0} Register Data Data Data S A A A A A .. A/Ā P Ex:00110100 Address (Reg. Address) (Reg. Address+1) (Reg. Address+2) S :From Master to Slave A :Acknowledge (SDA low) S :Start P :Stop Ā NO Acknowledge (SDA high) Figure 1-2 : An Example of Write Mode Procedure SCL SDA CONFIDENTIAL © 2012 by Rafael Microelectronics, Inc. All rights reserved. 3
When the slave address matches the I2C device ID with write control bit , I2C start interprets the following first byte as first written register address. These following bytes are all the register data (page write I2C control). Register 0 to Register 4 are reserved for internal use only and can be written by I2C write command. Figure 1-1 : The Typical Write Mode Sequence {Chip ID,0} Register Data Data Data S A A A A A .. A/Ā P Ex:00110100 Address (Reg. Address) (Reg. Address+1) (Reg. Address+2) S :From Master to Slave A :Acknowledge (SDA low) S :Start P :Stop Ā NO Acknowledge (SDA high) Figure 1-2 : An Example of Write Mode Procedure SCL SDA CONFIDENTIAL © 2012 by Rafael Microelectronics, Inc. All rights reserved. 3