Datasheet IRF9610 (Vishay) - 6
| Manufacturer | Vishay |
| Description | Power MOSFET in TO-220 package |
| Pages / Page | 7 / 6 — IRF9610. Fig. 18a - Basic Gate Charge Waveform. Fig. 18b - Gate Charge … |
| File Format / Size | PDF / 133 Kb |
| Document Language | English |
IRF9610. Fig. 18a - Basic Gate Charge Waveform. Fig. 18b - Gate Charge Test Circuit. Peak Diode Recovery dV/dt Test Circuit
Model Line for this Datasheet
Text Version of Document
IRF9610
www.vishay.com Vishay Siliconix Current regulator Same type as D.U.T. QG 15 V 50 kΩ 12 V 0.2 µF Q Q GS GD 0.3 µF - + VDS V D.U.T. G VGS Charge - 3 mA
Fig. 18a - Basic Gate Charge Waveform
I I G D Current sampling resistors
Fig. 18b - Gate Charge Test Circuit Peak Diode Recovery dV/dt Test Circuit D.U.T.
+ Circuit layout considerations • Low stray inductance • Ground plane • Low leakage inductance current transformer - + - - + Rg • dV/dt controlled by R + g • I V SD controlled by duty factor “D” - DD • D.U.T. - device under test
Note
• Compliment N-Channel of D.U.T. for driver Driver gate drive Period P.W. D = P.W. Period V = - 10 Va GS D.U.T. l waveform SD Reverse recovery Body diode forward current current dI/dt D.U.T. V waveform DS Diode recovery dV/dt VDD Re-applied voltage Body diode forward drop Inductor current I Ripple ≤ 5 % SD
Note
a. V = - 5 V for logic level and - 3 V drive devices GS
Fig. 19 - For P-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91080. S21-0867-Rev. C, 16-Aug-2021
6
Document Number: 91080 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
www.vishay.com Vishay Siliconix Current regulator Same type as D.U.T. QG 15 V 50 kΩ 12 V 0.2 µF Q Q GS GD 0.3 µF - + VDS V D.U.T. G VGS Charge - 3 mA
Fig. 18a - Basic Gate Charge Waveform
I I G D Current sampling resistors
Fig. 18b - Gate Charge Test Circuit Peak Diode Recovery dV/dt Test Circuit D.U.T.
+ Circuit layout considerations • Low stray inductance • Ground plane • Low leakage inductance current transformer - + - - + Rg • dV/dt controlled by R + g • I V SD controlled by duty factor “D” - DD • D.U.T. - device under test
Note
• Compliment N-Channel of D.U.T. for driver Driver gate drive Period P.W. D = P.W. Period V = - 10 Va GS D.U.T. l waveform SD Reverse recovery Body diode forward current current dI/dt D.U.T. V waveform DS Diode recovery dV/dt VDD Re-applied voltage Body diode forward drop Inductor current I Ripple ≤ 5 % SD
Note
a. V = - 5 V for logic level and - 3 V drive devices GS
Fig. 19 - For P-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91080. S21-0867-Rev. C, 16-Aug-2021
6
Document Number: 91080 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000