Datasheet J111, J112 (ON Semiconductor) - 3
| Manufacturer | ON Semiconductor |
| Description | JFET Chopper Transistors in TO-92 package |
| Pages / Page | 7 / 3 — J111, J112. TYPICAL SWITCHING CHARACTERISTICS. Figure 1. Turn−On Delay … |
| File Format / Size | PDF / 167 Kb |
| Document Language | English |
J111, J112. TYPICAL SWITCHING CHARACTERISTICS. Figure 1. Turn−On Delay Time. Figure 2. Rise Time. Figure 3. Turn−Off Delay Time
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J111, J112 TYPICAL SWITCHING CHARACTERISTICS
1000 1000 T TJ = 25°C 500 J = 25°C 500 J111 VGS(off) = 12 V (ns) R RK = RD′ K = RD′ J111 V J112 = 7.0 V 200 GS(off) = 12 V 200 J112 = 7.0 V J113 = 5.0 V TIME Y 100 J113 = 5.0 V 100 (ns) DELA 50 50 TIME 20 20 , RISE 10 t r 10 R , TURN−ON K = 0 5.0 RK = 0 5.0 t d(on) 2.0 2.0 1.0 1.0 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 30 50 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 30 50 ID, DRAIN CURRENT (mA) ID, DRAIN CURRENT (mA)
Figure 1. Turn−On Delay Time Figure 2. Rise Time
1000 1000 TJ = 25°C TJ = 25°C 500 500 (ns) J111 V RK = RD′ GS(off) = 12 V J111 VGS(off) = 12 V 200 J112 = 7.0 V 200 J112 = 7.0 V TIME Y 100 J113 = 5.0 V 100 J113 = 5.0 V (ns) DELA 50 RK = RD′ 50 TIME 20 ALL 20 R , F K = 0 10 t f 10 , TURN−OFF 5.0 RK = 0 5.0 t d(off) 2.0 2.0 1.0 1.0 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 30 50 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 30 50 ID, DRAIN CURRENT (mA) ID, DRAIN CURRENT (mA)
Figure 3. Turn−Off Delay Time Figure 4. Fall Time NOTE 1
+VDD The switching characteristics shown above were measured using a test circuit similar to Figure 5. At the beginning of the switching interval, RD the gate voltage is at Gate Supply Voltage (−VGG). The Drain−Source SET VDS(off) = 10 V Voltage (VDS) is slightly lower than Drain Supply Voltage (VDD) due INPUT to the voltage divider. Thus Reverse Transfer Capacitance (Crss) or RK RT Gate−Drain Capacitance (Cgd) is charged to VGG + VDS. RGEN OUTPUT During the turn−on interval, Gate−Source Capacitance (Cgs) 50 W RGG discharges through the series combination of RGen and RK. Cgd must 50 W 50 W discharge to VDS(on) through RG and RK in series with the parallel VGEN VGG combination of effective load impedance (R′D) and Drain−Source Resistance (rds). During the turn−off, this charge flow is reversed. Predicting turn−on time is somewhat difficult as the channel resistance INPUT PULSE RGG & RK rds is a function of the gate−source voltage. While Cgs discharges, VGS tr ≤ 0.25 ns approaches zero and rds decreases. Since Cgd discharges through rds, tf ≤ 0.5 ns RD(RT ) 50) RDȀ + turn−on time is non−linear. During turn−off, the situation is reversed PULSE WIDTH = 2.0 ms RD ) RT ) 50 DUTY CYCLE with r ≤ 2.0% ds increasing as Cgd charges. The above switching curves show two impedance conditions; 1) RK
Figure 5. Switching Time Test Circuit
is equal to RD, which simulates the switching behavior of cascaded stages where the driving source impedance is normally the load impedance of the previous stage, and 2) RK = 0 (low impedance) the driving source impedance is that of the generator.
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1000 1000 T TJ = 25°C 500 J = 25°C 500 J111 VGS(off) = 12 V (ns) R RK = RD′ K = RD′ J111 V J112 = 7.0 V 200 GS(off) = 12 V 200 J112 = 7.0 V J113 = 5.0 V TIME Y 100 J113 = 5.0 V 100 (ns) DELA 50 50 TIME 20 20 , RISE 10 t r 10 R , TURN−ON K = 0 5.0 RK = 0 5.0 t d(on) 2.0 2.0 1.0 1.0 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 30 50 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 30 50 ID, DRAIN CURRENT (mA) ID, DRAIN CURRENT (mA)
Figure 1. Turn−On Delay Time Figure 2. Rise Time
1000 1000 TJ = 25°C TJ = 25°C 500 500 (ns) J111 V RK = RD′ GS(off) = 12 V J111 VGS(off) = 12 V 200 J112 = 7.0 V 200 J112 = 7.0 V TIME Y 100 J113 = 5.0 V 100 J113 = 5.0 V (ns) DELA 50 RK = RD′ 50 TIME 20 ALL 20 R , F K = 0 10 t f 10 , TURN−OFF 5.0 RK = 0 5.0 t d(off) 2.0 2.0 1.0 1.0 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 30 50 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 30 50 ID, DRAIN CURRENT (mA) ID, DRAIN CURRENT (mA)
Figure 3. Turn−Off Delay Time Figure 4. Fall Time NOTE 1
+VDD The switching characteristics shown above were measured using a test circuit similar to Figure 5. At the beginning of the switching interval, RD the gate voltage is at Gate Supply Voltage (−VGG). The Drain−Source SET VDS(off) = 10 V Voltage (VDS) is slightly lower than Drain Supply Voltage (VDD) due INPUT to the voltage divider. Thus Reverse Transfer Capacitance (Crss) or RK RT Gate−Drain Capacitance (Cgd) is charged to VGG + VDS. RGEN OUTPUT During the turn−on interval, Gate−Source Capacitance (Cgs) 50 W RGG discharges through the series combination of RGen and RK. Cgd must 50 W 50 W discharge to VDS(on) through RG and RK in series with the parallel VGEN VGG combination of effective load impedance (R′D) and Drain−Source Resistance (rds). During the turn−off, this charge flow is reversed. Predicting turn−on time is somewhat difficult as the channel resistance INPUT PULSE RGG & RK rds is a function of the gate−source voltage. While Cgs discharges, VGS tr ≤ 0.25 ns approaches zero and rds decreases. Since Cgd discharges through rds, tf ≤ 0.5 ns RD(RT ) 50) RDȀ + turn−on time is non−linear. During turn−off, the situation is reversed PULSE WIDTH = 2.0 ms RD ) RT ) 50 DUTY CYCLE with r ≤ 2.0% ds increasing as Cgd charges. The above switching curves show two impedance conditions; 1) RK
Figure 5. Switching Time Test Circuit
is equal to RD, which simulates the switching behavior of cascaded stages where the driving source impedance is normally the load impedance of the previous stage, and 2) RK = 0 (low impedance) the driving source impedance is that of the generator.
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