Datasheet IP101G (IC Plus) - 4
| Manufacturer | IC Plus |
| Description | Single Port 10/100 MII/RMII/TP/Fiber Fast Ethernet Transceiver |
| Pages / Page | 66 / 4 — List of Figures |
| File Format / Size | PDF / 1.7 Mb |
| Document Language | English |
List of Figures
Model Line for this Datasheet
Text Version of Document
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List of Figures
Figure 1 Flow chart of IP101G ..8 Figure 2 IP101GA 48 Pin Top view Diagram ...9 Figure 3 IP101GR/GRI 32 Pin Top view Diagram ...10 Figure 4 IP101G dice pad information Top view.. 11 Figure 5 LPI transition ...43 Figure 6 IP101G/GA/GR/GRI MII Mode with LPI transition Block Diagram..43 Figure 7 IP101G/GA/GR/GRI MII Mode without LPI transition Block Diagram...43 Figure 8 IP101G RMII Mode with internal clock Block Diagram ...44 Figure 9 IP101G RMII Mode with external clock Block Diagram ..44 Figure 10 IP101GR need add a buffer if RXCLK/50M_CLK push over two device ..45 Figure 11 IP101G link speed and EEE ability programming guide ...46 Figure 12 PHY Address Configuration ..47 Figure 13 Magic Packet Format ..50 Figure 14 Sleep or wake up automatically programming guide ..51 Figure 15 MAC control sleep or wake up programming guide..52 Figure 16 MDC/MDIO Format ...54 Figure 17 IP101G Fiber Mode Setting...55 Figure 18 Reset, Pin Latched-In, Clock and Power Source Timing Requirements...59 Figure 19 MII Transmit Timing Requirements ...60 Figure 20 MII Receive Timing Specifications ..60 Figure 21 RMII Transmit Timing Requirements...61 Figure 22 RMII Receive Timing Specifications..61 Figure 23 SMI Timing Requirements...62 Figure 24 48-PIN LQFP Dimension...64 Figure 25 32-PIN QFN Dimension ..65 4/66 May 20, 2014 Copyright © 2011, IC Plus Corp. IP101G-DS-R01 Document Outline Features comparison between IP101G and IP101A/IP101AH 1 Pin diagram 2 Dice pad information 3 Pin description 3.1 IP101GA pin description 3.2 IP101GR/GRI pin description 4 Register Descriptions 4.1 Register Page mode Control Register 4.2 MII Registers 4.3 MMD Control Register 4.4 MMD Data Register 4.5 RX Counter Register 4.6 LED Pin Control Register 4.7 WOL+ Control Register 4.8 UTP PHY Specific Control Register 4.9 Digital IO Pin Control Register 5 Function Description 5.1 Major Functional Block Description 5.1.1 Transmission Description 5.1.2 MII and Management Control Interface 5.1.3 RMII Interface 5.1.4 Flexible Clock Source 5.1.5 Auto-Negotiation and Related Information 5.1.6 Auto-MDIX function 5.2 PHY Address Configuration 5.3 Power Management Tool 5.3.1 Auto Power Saving Mode 5.3.2 IEEE802.3az EEE (Energy Efficient Ethernet) 5.3.3 Force power down 5.3.4 WOL+ operation mode 5.4 LED Mode Configuration 5.5 LED Blink Timing 5.6 Repeater Mode 5.7 Interrupt 5.8 Miscellaneous 5.9 Serial Management Interface 5.10 Fiber Mode Setting 5.11 Jumbo Frame 6 Layout Guideline 6.1 General Layout Guideline 6.2 Twisted Pair recommendation 7 Electrical Characteristics 7.1 Absolute Maximum Rating 7.2 DC Characteristics 7.3 Crystal Specifications 7.4 AC Timing 7.4.1 Reset, Pin Latched-in, Clock and Power Source 7.4.2 MII Timing 7.4.3 RMII Timing 7.4.4 SMI Timing 7.4.5 MDI to MII latency delay time 7.5 Thermal Data 8 Order Information 9 Physical Dimensions 9.1 48-PIN LQFP 9.2 32-PIN QFN
List of Figures
Figure 1 Flow chart of IP101G ..8 Figure 2 IP101GA 48 Pin Top view Diagram ...9 Figure 3 IP101GR/GRI 32 Pin Top view Diagram ...10 Figure 4 IP101G dice pad information Top view.. 11 Figure 5 LPI transition ...43 Figure 6 IP101G/GA/GR/GRI MII Mode with LPI transition Block Diagram..43 Figure 7 IP101G/GA/GR/GRI MII Mode without LPI transition Block Diagram...43 Figure 8 IP101G RMII Mode with internal clock Block Diagram ...44 Figure 9 IP101G RMII Mode with external clock Block Diagram ..44 Figure 10 IP101GR need add a buffer if RXCLK/50M_CLK push over two device ..45 Figure 11 IP101G link speed and EEE ability programming guide ...46 Figure 12 PHY Address Configuration ..47 Figure 13 Magic Packet Format ..50 Figure 14 Sleep or wake up automatically programming guide ..51 Figure 15 MAC control sleep or wake up programming guide..52 Figure 16 MDC/MDIO Format ...54 Figure 17 IP101G Fiber Mode Setting...55 Figure 18 Reset, Pin Latched-In, Clock and Power Source Timing Requirements...59 Figure 19 MII Transmit Timing Requirements ...60 Figure 20 MII Receive Timing Specifications ..60 Figure 21 RMII Transmit Timing Requirements...61 Figure 22 RMII Receive Timing Specifications..61 Figure 23 SMI Timing Requirements...62 Figure 24 48-PIN LQFP Dimension...64 Figure 25 32-PIN QFN Dimension ..65 4/66 May 20, 2014 Copyright © 2011, IC Plus Corp. IP101G-DS-R01 Document Outline Features comparison between IP101G and IP101A/IP101AH 1 Pin diagram 2 Dice pad information 3 Pin description 3.1 IP101GA pin description 3.2 IP101GR/GRI pin description 4 Register Descriptions 4.1 Register Page mode Control Register 4.2 MII Registers 4.3 MMD Control Register 4.4 MMD Data Register 4.5 RX Counter Register 4.6 LED Pin Control Register 4.7 WOL+ Control Register 4.8 UTP PHY Specific Control Register 4.9 Digital IO Pin Control Register 5 Function Description 5.1 Major Functional Block Description 5.1.1 Transmission Description 5.1.2 MII and Management Control Interface 5.1.3 RMII Interface 5.1.4 Flexible Clock Source 5.1.5 Auto-Negotiation and Related Information 5.1.6 Auto-MDIX function 5.2 PHY Address Configuration 5.3 Power Management Tool 5.3.1 Auto Power Saving Mode 5.3.2 IEEE802.3az EEE (Energy Efficient Ethernet) 5.3.3 Force power down 5.3.4 WOL+ operation mode 5.4 LED Mode Configuration 5.5 LED Blink Timing 5.6 Repeater Mode 5.7 Interrupt 5.8 Miscellaneous 5.9 Serial Management Interface 5.10 Fiber Mode Setting 5.11 Jumbo Frame 6 Layout Guideline 6.1 General Layout Guideline 6.2 Twisted Pair recommendation 7 Electrical Characteristics 7.1 Absolute Maximum Rating 7.2 DC Characteristics 7.3 Crystal Specifications 7.4 AC Timing 7.4.1 Reset, Pin Latched-in, Clock and Power Source 7.4.2 MII Timing 7.4.3 RMII Timing 7.4.4 SMI Timing 7.4.5 MDI to MII latency delay time 7.5 Thermal Data 8 Order Information 9 Physical Dimensions 9.1 48-PIN LQFP 9.2 32-PIN QFN