Datasheet UCC34141-Q1 (Texas Instruments) - 9
| Manufacturer | Texas Instruments |
| Description | Automotive, 5.5V-to-20V VIN, 1.5W regulated 5kVRMS isolated DC/DC module with integrated transformer |
| Pages / Page | 41 / 9 — UCC34141-Q1. www.ti.com. 6.6 Electrical Characteristics (continued). … |
| File Format / Size | PDF / 2.3 Mb |
| Document Language | English |
UCC34141-Q1. www.ti.com. 6.6 Electrical Characteristics (continued). PARAMETER. TEST CONDITIONS. MIN. TYP. MAX. UNIT
Model Line for this Datasheet
Text Version of Document
UCC34141-Q1 www.ti.com
SLUSFP1D – APRIL 2024 – REVISED APRIL 2026
6.6 Electrical Characteristics (continued)
Over operating temperature range (TJ = –40°C to 150°C), unless otherwise noted. All typical values at TA = 25°C and VVIN = 12V. External BOM components are listed in the pin description table.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VENA_R Enable pin rising threshold Rising edge 1.425 1.5 1.575 V VENA_F Enable pin falling threshold Falling edge 1.282 1.35 1.418 V IENA Enable Pin Input Current VENA = 5.0V 5 10 µA Minimum period for EN = Low to reset tENA_LO_RST 400 µs latch off Minimum period required before EN = tENA_LO_DLY 200 µs Low to reset latch off
PG OPEN-DRAIN OUTPUT PIN (Primary-side. All voltages with respect to GNDP)
VPG_L PG output-low saturation voltage Sink Current = 5mA 0.5 V IPG_H PG Leakage current VPG = 5.5V 5 µA
PRIMARY-SIDE SOFT START
Deglitch time during soft start between VDD reaches regulation tPG_Delay 8.2 9.5 10.7 ms and Power-Good signal (PG) is issued.
Primary-side Control (All voltages with respect to GNDP)
V f VIN = 12V; VENA = 5V; (VDD- SW Switching frequency 16.5 MHz COM)=18V, (COM-VEE)=4V Timer begins when VIN > UVLOP and tSSTO Primary-side soft-start time-out ENA = High and reset when Power- 30 38 46 ms Good pin indicates Good
(VDD-COM) OUTPUT VOLTAGE (Secondary-side)
VVDD (VDD – COM) output voltage range 15 18 20 V Secondary-side (VDD – COM) output voltage accuracy at FBVDD, over load, (VDD – COM) output voltage DC line and temperature range, externally VVDD_REG -1.45 1.45 % regulation accuracy adjust with external resistor divider, within SOA range.
(VDD-COM) REGULATION HYSTERETIC COMPARATOR (Secondary-side)
Feedback regulation reference voltage VFBVDD_REF 2.473 2.51 2.547 rising threshold for (VDD – COM) Hysteresis at the FBVDD pin. VFBVDD_HYST The value represents peak-to-peak 16 20 24 mV magnitude.
(COM-VEE) REGULATION HYSTERETIC COMPARATOR (Secondary-side)
Hysteresis at the FBVEE pin. VFBVEE_HYST The value represents peak-to-peak 20 60 75 mV magnitude.
(VDD-COM) UVLOs COMPARATOR (Secondary-side)
(VDD – COM) undervoltage lockout VVDD_UVLOS_R Voltage from VDD to COM, rising 3.2 3.45 3.7 V rising threshold (VDD – COM) undervoltage lockout VVDD_UVLOS_F Voltage from VDD to COM, falling 3 3.25 3.5 V falling threshold
(VDD-COM) OVLOs COMPARATOR (Secondary-side)
(VDD – COM) over-voltage lockout VVDD_OVLOS_R Voltage from VDD to COM, rising 22.5 23 23.5 V rising threshold (VDD – COM) over-voltage lockout VVDD_OVLOS_F Voltage from VDD to COM, falling 21.7 22.2 22.7 V falling threshold
(VDD-COM) UVP, UNDER -VOLTAGE PROTECTION COMPARATOR (Secondary-side)
Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: UCC34141-Q1 Document Outline 1 Features 2 Applications 3 Description Table of Contents 4 Device Comparison 5 Pin Configuration and Functions 6 Specifications 6.1 Absolute Maximum Ratings 6.2 ESD Ratings 6.3 Recommended Operating Conditions 6.4 Thermal Information 6.5 Insulation Specifications 6.6 Electrical Characteristics 6.7 Safety Limiting Values 6.8 Typical Characteristics 7 Detailed Description 7.1 Overview 7.2 Functional Block Diagram 7.3 Feature Description 7.3.1 Power Stage Operation 7.3.1.1 VDD-COM Voltage Regulation 7.3.1.2 COM-VEE Voltage Regulation 7.3.1.3 COM-VEE Output Capability 7.3.2 Output Voltage Soft Start 7.3.3 ENA and Power-Good 7.3.4 Protection Functions 7.3.4.1 Input Undervoltage Lockout 7.3.4.2 Input Overvoltage Lockout 7.3.4.3 Output Undervoltage Protection 7.3.4.4 Output Overvoltage Protection 7.3.4.5 Output Short Circuit Protection 7.3.4.6 Over-Temperature Protection 7.3.4.7 BSW Pin Faults Protection 7.4 Device Functional Modes 8 Application and Implementation 8.1 Application Information 8.2 Typical Application 8.2.1 Design Requirements 8.2.2 Detailed Design Procedure 8.2.2.1 VDD-COM Voltage Regulation 8.2.2.2 COM-VEE Voltage Regulation and Single Output Configuration 8.3 System Examples 8.4 Power Supply Recommendations 8.5 Layout 8.5.1 Layout Guidelines 8.5.2 Layout Example 9 Device and Documentation Support 9.1 Third-Party Products Disclaimer 9.2 Documentation Support 9.2.1 Related Documentation 9.3 Receiving Notification of Documentation Updates 9.4 Support Resources 9.5 Trademarks 9.6 Electrostatic Discharge Caution 9.7 Glossary 10 Revision History 11 Mechanical, Packaging, and Orderable Information
SLUSFP1D – APRIL 2024 – REVISED APRIL 2026
6.6 Electrical Characteristics (continued)
Over operating temperature range (TJ = –40°C to 150°C), unless otherwise noted. All typical values at TA = 25°C and VVIN = 12V. External BOM components are listed in the pin description table.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VENA_R Enable pin rising threshold Rising edge 1.425 1.5 1.575 V VENA_F Enable pin falling threshold Falling edge 1.282 1.35 1.418 V IENA Enable Pin Input Current VENA = 5.0V 5 10 µA Minimum period for EN = Low to reset tENA_LO_RST 400 µs latch off Minimum period required before EN = tENA_LO_DLY 200 µs Low to reset latch off
PG OPEN-DRAIN OUTPUT PIN (Primary-side. All voltages with respect to GNDP)
VPG_L PG output-low saturation voltage Sink Current = 5mA 0.5 V IPG_H PG Leakage current VPG = 5.5V 5 µA
PRIMARY-SIDE SOFT START
Deglitch time during soft start between VDD reaches regulation tPG_Delay 8.2 9.5 10.7 ms and Power-Good signal (PG) is issued.
Primary-side Control (All voltages with respect to GNDP)
V f VIN = 12V; VENA = 5V; (VDD- SW Switching frequency 16.5 MHz COM)=18V, (COM-VEE)=4V Timer begins when VIN > UVLOP and tSSTO Primary-side soft-start time-out ENA = High and reset when Power- 30 38 46 ms Good pin indicates Good
(VDD-COM) OUTPUT VOLTAGE (Secondary-side)
VVDD (VDD – COM) output voltage range 15 18 20 V Secondary-side (VDD – COM) output voltage accuracy at FBVDD, over load, (VDD – COM) output voltage DC line and temperature range, externally VVDD_REG -1.45 1.45 % regulation accuracy adjust with external resistor divider, within SOA range.
(VDD-COM) REGULATION HYSTERETIC COMPARATOR (Secondary-side)
Feedback regulation reference voltage VFBVDD_REF 2.473 2.51 2.547 rising threshold for (VDD – COM) Hysteresis at the FBVDD pin. VFBVDD_HYST The value represents peak-to-peak 16 20 24 mV magnitude.
(COM-VEE) REGULATION HYSTERETIC COMPARATOR (Secondary-side)
Hysteresis at the FBVEE pin. VFBVEE_HYST The value represents peak-to-peak 20 60 75 mV magnitude.
(VDD-COM) UVLOs COMPARATOR (Secondary-side)
(VDD – COM) undervoltage lockout VVDD_UVLOS_R Voltage from VDD to COM, rising 3.2 3.45 3.7 V rising threshold (VDD – COM) undervoltage lockout VVDD_UVLOS_F Voltage from VDD to COM, falling 3 3.25 3.5 V falling threshold
(VDD-COM) OVLOs COMPARATOR (Secondary-side)
(VDD – COM) over-voltage lockout VVDD_OVLOS_R Voltage from VDD to COM, rising 22.5 23 23.5 V rising threshold (VDD – COM) over-voltage lockout VVDD_OVLOS_F Voltage from VDD to COM, falling 21.7 22.2 22.7 V falling threshold
(VDD-COM) UVP, UNDER -VOLTAGE PROTECTION COMPARATOR (Secondary-side)
Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: UCC34141-Q1 Document Outline 1 Features 2 Applications 3 Description Table of Contents 4 Device Comparison 5 Pin Configuration and Functions 6 Specifications 6.1 Absolute Maximum Ratings 6.2 ESD Ratings 6.3 Recommended Operating Conditions 6.4 Thermal Information 6.5 Insulation Specifications 6.6 Electrical Characteristics 6.7 Safety Limiting Values 6.8 Typical Characteristics 7 Detailed Description 7.1 Overview 7.2 Functional Block Diagram 7.3 Feature Description 7.3.1 Power Stage Operation 7.3.1.1 VDD-COM Voltage Regulation 7.3.1.2 COM-VEE Voltage Regulation 7.3.1.3 COM-VEE Output Capability 7.3.2 Output Voltage Soft Start 7.3.3 ENA and Power-Good 7.3.4 Protection Functions 7.3.4.1 Input Undervoltage Lockout 7.3.4.2 Input Overvoltage Lockout 7.3.4.3 Output Undervoltage Protection 7.3.4.4 Output Overvoltage Protection 7.3.4.5 Output Short Circuit Protection 7.3.4.6 Over-Temperature Protection 7.3.4.7 BSW Pin Faults Protection 7.4 Device Functional Modes 8 Application and Implementation 8.1 Application Information 8.2 Typical Application 8.2.1 Design Requirements 8.2.2 Detailed Design Procedure 8.2.2.1 VDD-COM Voltage Regulation 8.2.2.2 COM-VEE Voltage Regulation and Single Output Configuration 8.3 System Examples 8.4 Power Supply Recommendations 8.5 Layout 8.5.1 Layout Guidelines 8.5.2 Layout Example 9 Device and Documentation Support 9.1 Third-Party Products Disclaimer 9.2 Documentation Support 9.2.1 Related Documentation 9.3 Receiving Notification of Documentation Updates 9.4 Support Resources 9.5 Trademarks 9.6 Electrostatic Discharge Caution 9.7 Glossary 10 Revision History 11 Mechanical, Packaging, and Orderable Information