Datasheet EPC23110 (Efficient Power Conversion) - 7
| Manufacturer | Efficient Power Conversion |
| Description | 100V, 20 A ePower Stage IC |
| Pages / Page | 17 / 7 — eGaN® IC DATASHEET. Typical Output Charge and COSS Stored Energy Figure … |
| File Format / Size | PDF / 2.0 Mb |
| Document Language | English |
eGaN® IC DATASHEET. Typical Output Charge and COSS Stored Energy Figure 5a: QOSS and EOSS of High-Side Power GaN FET
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eGaN® IC DATASHEET
EPC23110
Typical Output Charge and COSS Stored Energy Figure 5a: QOSS and EOSS of High-Side Power GaN FET Figure 5b: QOSS and EOSS of Low-Side Power GaN FET
35 1.5 35 1.5 28 1.2
) ) )
28 1.2
) gy (μJ gy (μJ ge (nC ge (nC
21 0.9
har
21 0.9
har ed Ener ed Ener tor tor utput C S utput C S
14 0.6 14 0.6
− O OSS − O OSS − C − C OSS OSS Q Q
7 0.3
E OSS
7 0.3
E OSS
0 0.0 0 0.0 0 25 50 75 100 0 25 50 75 100
VDS − Drain-to-Source Voltage (V) VDS − Drain-to-Source Voltage (V) Power GaN FETs Typical RDS(on) vs. Temperature Figure 6a: High Side FET Normalized RDS(on) Figure 6b: Low Side FET Normalized RDS(on)
1.8 1.8 1.6 1.6 1.4 1.4
(mΩ) (mΩ)
1.2 1.2
R DS(on)_HS
1.0
R DS(on)_LS
1.0 0.8 0.8 0.6 0.6 -50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
Temperature (°C) Temperature (°C) Truth Table SD/STB VDD VBOOT – VPHASE HSIN LSIN HS FET LS FET
Low(1) – – – – OFF OFF <VDD_POR – - - OFF OFF – 0 OFF OFF >VDD_POR <VBOOT_POR – 1 OFF ON High 0 0 OFF OFF 0 1 OFF ON >VDD_POR >VBOOT_POR 1 0 ON OFF 1 1 OFF OFF (1) SD/STB immediately inhibits PWM inputs when pul ed low. EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2026 | For more information: info@epc-co.com | 7
EPC23110
Typical Output Charge and COSS Stored Energy Figure 5a: QOSS and EOSS of High-Side Power GaN FET Figure 5b: QOSS and EOSS of Low-Side Power GaN FET
35 1.5 35 1.5 28 1.2
) ) )
28 1.2
) gy (μJ gy (μJ ge (nC ge (nC
21 0.9
har
21 0.9
har ed Ener ed Ener tor tor utput C S utput C S
14 0.6 14 0.6
− O OSS − O OSS − C − C OSS OSS Q Q
7 0.3
E OSS
7 0.3
E OSS
0 0.0 0 0.0 0 25 50 75 100 0 25 50 75 100
VDS − Drain-to-Source Voltage (V) VDS − Drain-to-Source Voltage (V) Power GaN FETs Typical RDS(on) vs. Temperature Figure 6a: High Side FET Normalized RDS(on) Figure 6b: Low Side FET Normalized RDS(on)
1.8 1.8 1.6 1.6 1.4 1.4
(mΩ) (mΩ)
1.2 1.2
R DS(on)_HS
1.0
R DS(on)_LS
1.0 0.8 0.8 0.6 0.6 -50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
Temperature (°C) Temperature (°C) Truth Table SD/STB VDD VBOOT – VPHASE HSIN LSIN HS FET LS FET
Low(1) – – – – OFF OFF <VDD_POR – - - OFF OFF – 0 OFF OFF >VDD_POR <VBOOT_POR – 1 OFF ON High 0 0 OFF OFF 0 1 OFF ON >VDD_POR >VBOOT_POR 1 0 ON OFF 1 1 OFF OFF (1) SD/STB immediately inhibits PWM inputs when pul ed low. EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2026 | For more information: info@epc-co.com | 7