Datasheet LT8418 (Analog Devices) - 4
| Manufacturer | Analog Devices |
| Description | 100V Half-Bridge GaN Driver with Smart Integrated Bootstrap Switch in WLCSP-12 package |
| Pages / Page | 19 / 4 — Data Sheet. LT8418. PARAMETER. SYMBOL. CONDITIONS/COMMENTS. MIN. TYP. … |
| File Format / Size | PDF / 697 Kb |
| Document Language | English |
Data Sheet. LT8418. PARAMETER. SYMBOL. CONDITIONS/COMMENTS. MIN. TYP. MAX. UNITS
Model Line for this Datasheet
Text Version of Document
Data Sheet LT8418
(TA = 25°C1, VCC = VBST = 5V, VGND = VSW = 0V; TGP and TGN are connected; BGP and BGN are connected)
PARAMETER SYMBOL CONDITIONS/COMMENTS MIN TYP MAX UNITS
TG Rise Time tTGR CL = 1nF, 10% to 90% 2.5 ns TG Fall Time tTGF CL = 1nF, 90% to 10% 2.5 ns BG Rise Time tBGR CL = 1nF, 10% to 90% 2.5 ns BG Fall Time tBGF CL = 1nF, 90% to 10% 2.5 ns
Propagation Delay, Delay Matching, and Minimum Input Pulse2
TG Turn-On INT Rising to TG Rising (TGP = TGN = t 10 16 ns Propagation Delay RPD_TG TG) TG Turn-Off t Propagation Delay FPD_TG INT Falling to TG Falling 10 15 ns BG Turn-On INB Rising to BG Rising (BGP = BGN = t 10 16 ns Propagation Delay RPD_BG BG) BG Turn-Off t Propagation Delay FPD_BG INB Falling to BG Falling 10 15 ns TG Turn-Off and BG Turn-On Delay tDMF 0.5 5 ns Mismatch BG Turn-Off and TG Turn-On Delay tDMR 0.5 6.5 ns Mismatch TG, BG Minimum Input t Pulse Width TGW, tBGW 11 ns . 1 The LT8418 is tested under pulsed load conditions such that TJ ≈ TA. The LT8418A is guaranteed to meet specifications from –40°C to 125°C junction temperature. High junction temperatures degrade operating lifetimes; operating lifetime is derated for junction temperatures greater than 125°C. Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance, and other environmental factors. The junction temperature (TJ, in °C) is calculated from the ambient temperature (TA, in °C) and power dissipation (PD, in Watts) according to the formula: TJ = TA + (PD × JA), where θJA (in °C/W) is the package thermal impedance. 2 The definition of propagation delay for the top or bottom side gate driver and delay matching is illustrated in the following timing diagram.
analog.com
Rev 0 4 of 19 Document Outline Features Applications General Description Typical Application TABLE OF CONTENTS Revision History Specifications Timing Diagrams Absolute Maximum Ratings Thermal Resistance Pin Configurations and Function Descriptions Pin Descriptions Block diagram Typical Performance Characteristics Theory of Operation 1.1. Chip Start-up, VCC UVLO/OVLO Protections 1.2. Input Interface INT, INB 1.3. Smart Bootstrap (BST) Switch and BST UVLO 1.4. Split Gate Driver Applications Information 1.1. Selecting the VCC and BST Capacitor 1.2. Selecting the Gate Resistance 1.3. Power Dissipation 1.4. PCB Bypass and Grounding Guideline 1.5. Soldering Guideline Outline Dimensions Typical Applications Ordering Guide Related Parts
(TA = 25°C1, VCC = VBST = 5V, VGND = VSW = 0V; TGP and TGN are connected; BGP and BGN are connected)
PARAMETER SYMBOL CONDITIONS/COMMENTS MIN TYP MAX UNITS
TG Rise Time tTGR CL = 1nF, 10% to 90% 2.5 ns TG Fall Time tTGF CL = 1nF, 90% to 10% 2.5 ns BG Rise Time tBGR CL = 1nF, 10% to 90% 2.5 ns BG Fall Time tBGF CL = 1nF, 90% to 10% 2.5 ns
Propagation Delay, Delay Matching, and Minimum Input Pulse2
TG Turn-On INT Rising to TG Rising (TGP = TGN = t 10 16 ns Propagation Delay RPD_TG TG) TG Turn-Off t Propagation Delay FPD_TG INT Falling to TG Falling 10 15 ns BG Turn-On INB Rising to BG Rising (BGP = BGN = t 10 16 ns Propagation Delay RPD_BG BG) BG Turn-Off t Propagation Delay FPD_BG INB Falling to BG Falling 10 15 ns TG Turn-Off and BG Turn-On Delay tDMF 0.5 5 ns Mismatch BG Turn-Off and TG Turn-On Delay tDMR 0.5 6.5 ns Mismatch TG, BG Minimum Input t Pulse Width TGW, tBGW 11 ns . 1 The LT8418 is tested under pulsed load conditions such that TJ ≈ TA. The LT8418A is guaranteed to meet specifications from –40°C to 125°C junction temperature. High junction temperatures degrade operating lifetimes; operating lifetime is derated for junction temperatures greater than 125°C. Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance, and other environmental factors. The junction temperature (TJ, in °C) is calculated from the ambient temperature (TA, in °C) and power dissipation (PD, in Watts) according to the formula: TJ = TA + (PD × JA), where θJA (in °C/W) is the package thermal impedance. 2 The definition of propagation delay for the top or bottom side gate driver and delay matching is illustrated in the following timing diagram.
analog.com
Rev 0 4 of 19 Document Outline Features Applications General Description Typical Application TABLE OF CONTENTS Revision History Specifications Timing Diagrams Absolute Maximum Ratings Thermal Resistance Pin Configurations and Function Descriptions Pin Descriptions Block diagram Typical Performance Characteristics Theory of Operation 1.1. Chip Start-up, VCC UVLO/OVLO Protections 1.2. Input Interface INT, INB 1.3. Smart Bootstrap (BST) Switch and BST UVLO 1.4. Split Gate Driver Applications Information 1.1. Selecting the VCC and BST Capacitor 1.2. Selecting the Gate Resistance 1.3. Power Dissipation 1.4. PCB Bypass and Grounding Guideline 1.5. Soldering Guideline Outline Dimensions Typical Applications Ordering Guide Related Parts