Datasheet DCL540C01A (Toshiba) - 9
| Manufacturer | Toshiba |
| Description | High Speed Quad Channel Digital Isolators |
| Pages / Page | 38 / 9 — 9.2. Electrical Characteristics – 3.3 V Supply |
| File Format / Size | PDF / 1.4 Mb |
| Document Language | English |
9.2. Electrical Characteristics – 3.3 V Supply
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9.2. Electrical Characteristics – 3.3 V Supply
All typical specifications are at Ta=25 °C, VDD1=VDD2=3.3 V. Minimum/maximum specifications apply over the entire recommended operating range of 3.0 V≤VDD1≤3.6 V, 3.0 V≤VDD2≤3.6 V, and -40 °C≤Ta≤125 °C, unless otherwise noted. PARAMETER TEST CONDITIONS Fig. SYMBOL MIN TYP. MAX UNIT DC SPECIFICATIONS Threshold when supply V voltage is rising DDxUV+ - 2.1 2.25 Under voltage Lockout Threshold when supply 12.1 V V voltage is falling DDxUV- 1.7 1.9 - Supply voltage hysteresis VDDxUVH 0.1 0.2 - VDDO-0.1 VDDO Output Voltage VIx=H , IOH=-20 μA (Note1) (Note1) - 12.2 V V Logic High OH V VDDO-0.2 Ix=H , IOH=-4 mA VDDO-0.4 (Note1) (Note1) - Output Voltage VIx=L , IOL =20 μA - 0.0 0.1 12.2 V V Logic Low OL VIx=L , IOL =4 mA - 0.2 0.4 Output impedance - 12.2 ZO - 50 - Ω High-level input voltage - 12.3 VIH 0.7*VDDI (Note1) - - V Low-level input voltage - 12.3 VIL - - 0.3*VDDI (Note1) V Input Voltage Hysteresis - 12.3 VHYS - 0.32 - V Input Current VI= VDDI or 0 V (Note1) - II - - ±10 μA SWITCHING SPECIFICATIONS Data Rate - - tbps DC - 150 Mbps Pulse Width - - PW 6.6 - - ns 50 kHz,Duty=50 %, Propagation Delay 12.4 t t pHL , tpLH - 11.6 19.1 ns r=tf=2 ns,CL=15 pF Pulse Width Distortion |tPHL – tPLH| 12.4 PWD - 0.8 2.8 ns Propagation Delay Skew (Between any two units) (Note 2) - tPSK - - 10 ns Same Direction 12.4 tskCD - - 3.3 Channel Matching ns Opposing Direction 12.4 tskOD - - 3.7 Output Rise Time 10 % - 90 % 12.4 tr - 0.8 - ns Output Fall Time 90 % - 10 % 12.4 tf - 0.8 - ns Enable 3-state output 50 kHz, Duty=50 %, 12.5 t enable time pZL , tpZH - - 15.0 ns tr=tf=2 ns,CL=15 pF Enable 3-state output (Note 3) 12.5 t disable time pLZ , tpHZ - - 18.0 ns Disable output enable time 12.6 t 50 kHz, Duty=50 %, p_EN , - - 23.0 ns tr=tf=2 ns,CL=15 pF Disable output disable time 12.6 tp_DIS - - 23.0 ns Common mode transient VI= VDDI or 0 V, (Note1) 12.7 | CMTI | - 150 - kV/μs immunity VCM=1500 V, Ta=25 °C Note 1: VDDI=Input-side VDDx , VDDO=Output-side VDDx Note 2: Propagation delay difference (between parts) is applied under the same operating conditions (power supply voltage. input current, temperature conditions, etc.). Note 3: When ENx signal is changed from Low to High or OPEN, the output signal(VOx) is valid after the output enable time. The output signal(VOx) within the output enable time is undefined) 9 2026-07-14 ©2026 Toshiba Electronic Devices & Storage Corporation Rev.1.4
9.2. Electrical Characteristics – 3.3 V Supply
All typical specifications are at Ta=25 °C, VDD1=VDD2=3.3 V. Minimum/maximum specifications apply over the entire recommended operating range of 3.0 V≤VDD1≤3.6 V, 3.0 V≤VDD2≤3.6 V, and -40 °C≤Ta≤125 °C, unless otherwise noted. PARAMETER TEST CONDITIONS Fig. SYMBOL MIN TYP. MAX UNIT DC SPECIFICATIONS Threshold when supply V voltage is rising DDxUV+ - 2.1 2.25 Under voltage Lockout Threshold when supply 12.1 V V voltage is falling DDxUV- 1.7 1.9 - Supply voltage hysteresis VDDxUVH 0.1 0.2 - VDDO-0.1 VDDO Output Voltage VIx=H , IOH=-20 μA (Note1) (Note1) - 12.2 V V Logic High OH V VDDO-0.2 Ix=H , IOH=-4 mA VDDO-0.4 (Note1) (Note1) - Output Voltage VIx=L , IOL =20 μA - 0.0 0.1 12.2 V V Logic Low OL VIx=L , IOL =4 mA - 0.2 0.4 Output impedance - 12.2 ZO - 50 - Ω High-level input voltage - 12.3 VIH 0.7*VDDI (Note1) - - V Low-level input voltage - 12.3 VIL - - 0.3*VDDI (Note1) V Input Voltage Hysteresis - 12.3 VHYS - 0.32 - V Input Current VI= VDDI or 0 V (Note1) - II - - ±10 μA SWITCHING SPECIFICATIONS Data Rate - - tbps DC - 150 Mbps Pulse Width - - PW 6.6 - - ns 50 kHz,Duty=50 %, Propagation Delay 12.4 t t pHL , tpLH - 11.6 19.1 ns r=tf=2 ns,CL=15 pF Pulse Width Distortion |tPHL – tPLH| 12.4 PWD - 0.8 2.8 ns Propagation Delay Skew (Between any two units) (Note 2) - tPSK - - 10 ns Same Direction 12.4 tskCD - - 3.3 Channel Matching ns Opposing Direction 12.4 tskOD - - 3.7 Output Rise Time 10 % - 90 % 12.4 tr - 0.8 - ns Output Fall Time 90 % - 10 % 12.4 tf - 0.8 - ns Enable 3-state output 50 kHz, Duty=50 %, 12.5 t enable time pZL , tpZH - - 15.0 ns tr=tf=2 ns,CL=15 pF Enable 3-state output (Note 3) 12.5 t disable time pLZ , tpHZ - - 18.0 ns Disable output enable time 12.6 t 50 kHz, Duty=50 %, p_EN , - - 23.0 ns tr=tf=2 ns,CL=15 pF Disable output disable time 12.6 tp_DIS - - 23.0 ns Common mode transient VI= VDDI or 0 V, (Note1) 12.7 | CMTI | - 150 - kV/μs immunity VCM=1500 V, Ta=25 °C Note 1: VDDI=Input-side VDDx , VDDO=Output-side VDDx Note 2: Propagation delay difference (between parts) is applied under the same operating conditions (power supply voltage. input current, temperature conditions, etc.). Note 3: When ENx signal is changed from Low to High or OPEN, the output signal(VOx) is valid after the output enable time. The output signal(VOx) within the output enable time is undefined) 9 2026-07-14 ©2026 Toshiba Electronic Devices & Storage Corporation Rev.1.4