Datasheet ACT 1 (Actel) - 2
| Manufacturer | Actel |
| Description | ACT 1 Series FPGAs |
| Pages / Page | 24 / 2 — Figure 1 •. A C T 1 D e v i c e S t r u c t u r e. T h e A C T 1 L o g i … |
| File Format / Size | PDF / 109 Kb |
| Document Language | English |
Figure 1 •. A C T 1 D e v i c e S t r u c t u r e. T h e A C T 1 L o g i c M o d u l e. Figure 2 •. I / O B u f f e r s. 1-284
Text Version of Document
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The systems are available for 386/486/Pentium™ PC and for Mentor Graphics®, Cadence™, OrCAD™, and Synopsys HP™ and Sun™ workstations and for running Viewlogic®, design environments.
Figure 1 •
Partial View of an ACT 1 Device
A C T 1 D e v i c e S t r u c t u r e
A partial view of an ACT 1 device (Figure 1) depicts four logic modules and distributed horizontal and vertical interconnect tracks. PLICE antifuses, located at intersections of the horizontal and vertical tracks, connect logic module inputs and outputs. During programming, these antifuses are addressed and programmed to make the connections required by the circuit application.
T h e A C T 1 L o g i c M o d u l e
The ACT 1 logic module is an 8-input, one-output logic circuit chosen for the wide range of functions it implements and for its efficient use of interconnect routing resources (Figure 2). The logic module can implement the four basic logic functions (NAND, AND, OR, and NOR) in gates of two, three, or four inputs. Each function may have many versions, with different combinations of active-low inputs. The logic module can also implement a variety of D-latches, exclusivity functions, AND-ORs, and OR-ANDs. No dedicated hardwired latches or flip-flops are required in the array, since latches
Figure 2 •
ACT 1 Logic Module and flip-flops may be constructed from logic modules wherever needed in the application.
I / O B u f f e r s
Each I/O pin is available as an input, output, three-state, or bidirectional buffer. Input and output levels are compatible with standard TTL and CMOS specifications. Outputs sink or
1-284
Document Outline ACT™ 1 Series FPGAs Features Description Product Family Profile The Designer and Designer Advantage™ Systems ACT 1 Device Structure The ACT 1 Logic Module I/O Buffers Device Organization Probe Pin ACT 1 Array Performance Temperature and Voltage Effects Logic Module Size Ordering Information Product Plan Device Resources Pin Description Absolute Maximum Ratings1 Free air temperature range Recommended Operating Conditions Electrical Specifications (5V) Electrical Specifications (3.3V) Package Thermal Characteristics General Power Equation Static Power Component Active Power Component Equivalent Capacitance CEQ Values for Actel FPGAs Fixed Capacitance Values for Actel FPGAs (pF) Determining Average Switching Frequency Functional Timing Tests Output Buffer Performance Derating (5V) Output Buffer Performance Derating (3.3V) ACT 1 Timing Module* Predictable Performance: Tight Delay Distributions... Timing Characteristics Critical Nets and Typical Nets Long Tracks Timing Derating Timing Derating Factor (Temperature and Voltage) Timing Derating Factor for Designs at Typical Temp... Temperature and Voltage Derating Factors (normaliz... Temperature and Voltage Derating Factors (normaliz... Junction Temperature and Voltage Derating Curves (... Parameter Measurement Output Buffer Delays AC Test Loads Input Buffer Delays Module Delays Sequential Timing Characteristics Flip-Flops and Latches ACT 1 Timing Characteristics (Worst-Case Commercial Conditions, VCC = 4.75 V,T... ACT 1 Timing Characteristics (continued) (Worst-Case Commercial Conditions) ACT 1 Timing Characteristics (continued) (Worst-Case Commercial Conditions) Package Pin Assignments 44-Pin PLCC 68-Pin PLCC Package Pin Assignments (continued) 84-Pin PLCC Package Pin Assignments (continued) 100-Pin PQFP Package Pin Assignments (continued) 80-Pin VQFP Package Pin Assignments (continued) 84-Pin CPGA Package Pin Assignments (continued) 84-Pin CQFP
The systems are available for 386/486/Pentium™ PC and for Mentor Graphics®, Cadence™, OrCAD™, and Synopsys HP™ and Sun™ workstations and for running Viewlogic®, design environments.
Figure 1 •
Partial View of an ACT 1 Device
A C T 1 D e v i c e S t r u c t u r e
A partial view of an ACT 1 device (Figure 1) depicts four logic modules and distributed horizontal and vertical interconnect tracks. PLICE antifuses, located at intersections of the horizontal and vertical tracks, connect logic module inputs and outputs. During programming, these antifuses are addressed and programmed to make the connections required by the circuit application.
T h e A C T 1 L o g i c M o d u l e
The ACT 1 logic module is an 8-input, one-output logic circuit chosen for the wide range of functions it implements and for its efficient use of interconnect routing resources (Figure 2). The logic module can implement the four basic logic functions (NAND, AND, OR, and NOR) in gates of two, three, or four inputs. Each function may have many versions, with different combinations of active-low inputs. The logic module can also implement a variety of D-latches, exclusivity functions, AND-ORs, and OR-ANDs. No dedicated hardwired latches or flip-flops are required in the array, since latches
Figure 2 •
ACT 1 Logic Module and flip-flops may be constructed from logic modules wherever needed in the application.
I / O B u f f e r s
Each I/O pin is available as an input, output, three-state, or bidirectional buffer. Input and output levels are compatible with standard TTL and CMOS specifications. Outputs sink or
1-284
Document Outline ACT™ 1 Series FPGAs Features Description Product Family Profile The Designer and Designer Advantage™ Systems ACT 1 Device Structure The ACT 1 Logic Module I/O Buffers Device Organization Probe Pin ACT 1 Array Performance Temperature and Voltage Effects Logic Module Size Ordering Information Product Plan Device Resources Pin Description Absolute Maximum Ratings1 Free air temperature range Recommended Operating Conditions Electrical Specifications (5V) Electrical Specifications (3.3V) Package Thermal Characteristics General Power Equation Static Power Component Active Power Component Equivalent Capacitance CEQ Values for Actel FPGAs Fixed Capacitance Values for Actel FPGAs (pF) Determining Average Switching Frequency Functional Timing Tests Output Buffer Performance Derating (5V) Output Buffer Performance Derating (3.3V) ACT 1 Timing Module* Predictable Performance: Tight Delay Distributions... Timing Characteristics Critical Nets and Typical Nets Long Tracks Timing Derating Timing Derating Factor (Temperature and Voltage) Timing Derating Factor for Designs at Typical Temp... Temperature and Voltage Derating Factors (normaliz... Temperature and Voltage Derating Factors (normaliz... Junction Temperature and Voltage Derating Curves (... Parameter Measurement Output Buffer Delays AC Test Loads Input Buffer Delays Module Delays Sequential Timing Characteristics Flip-Flops and Latches ACT 1 Timing Characteristics (Worst-Case Commercial Conditions, VCC = 4.75 V,T... ACT 1 Timing Characteristics (continued) (Worst-Case Commercial Conditions) ACT 1 Timing Characteristics (continued) (Worst-Case Commercial Conditions) Package Pin Assignments 44-Pin PLCC 68-Pin PLCC Package Pin Assignments (continued) 84-Pin PLCC Package Pin Assignments (continued) 100-Pin PQFP Package Pin Assignments (continued) 80-Pin VQFP Package Pin Assignments (continued) 84-Pin CPGA Package Pin Assignments (continued) 84-Pin CQFP
