Datasheet AD8330 (Analog Devices) - 8
| Manufacturer | Analog Devices |
| Description | Low Cost, DC to 150 MHz, Variable Gain Amplifier |
| Pages / Page | 32 / 8 — AD8330. Data Sheet. VMAG = 4.8V. 1048 UNITS. ENABLE MODE. 1.52V. 0.48V. … |
| Revision | H |
| File Format / Size | PDF / 1.4 Mb |
| Document Language | English |
AD8330. Data Sheet. VMAG = 4.8V. 1048 UNITS. ENABLE MODE. 1.52V. 0.48V. 0.15V. ITS. 0.048V. N ( AI. 0.015V. OF U. % 10. –10. –20. –30. –40. 100k. 10M. 100M. 500M
Model Line for this Datasheet
Text Version of Document
AD8330 Data Sheet 50 25 VMAG = 4.8V 1048 UNITS 40 ENABLE MODE 1.52V 20 30 0.48V 20 0.15V 15 B) ITS d 10 0.048V N N ( AI 0 0.015V OF U G % 10 –10 –20 5 –30 –40 0
011
9 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 9 0
014
100k 1M 10M 100M 500M 0. 0. 0. 0. 0. 0. 0. 0. 0. 1. –0. –0. –0. –0. –0. –0. –0. –0. –0. FREQUENCY (Hz)
03217-
DIFFERENTIAL OFFSET (mV)
03217- Figure 10. Frequency Response for Various Values of VMAG, Figure 13. Differential Input Offset Histogram VDBS = 0.75 V
10 10 VDBS = 0.1V 0 8 B) –10 d ) R ( –20 s RRO Y (n 6 –30 A E L –40 DE ANCE UP 4 AL O –50 B R G UT P –60 UT 2 O –70 –80 0 –90 100k 1M 10M 100M 300M
012
100k 1M 10M 100M
015
FREQUENCY (Hz)
03217-
FREQUENCY (Hz)
03217- Figure 11. Group Delay vs. Frequency Figure 14. Output Balance Error vs. Frequency for a Representative Part
0 200 190 –1 180 V) –2 Ω) 170 T = –40°C ( E (m 160 G –3 A DANCE LT E 150 O P V M T –4 T = +25°C I E 140 UT P OFFS –5 UT 130 O 120 –6 T = +85°C 110 –7 100 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
013
100k M 1 M 0 1 100M 0 3 M 0
016
VDBS (V)
03217-
FREQUENCY (Hz)
03217- Figure 12. Differential Output Offset vs. VDBS for Three Temperatures, Figure 15. Output Impedance vs. Frequency for a Representative Part Rev. G | Page 8 of 32 Document Outline Features Applications Functional Block Diagram General Description Table of Contents Revision History Specifications Absolute Maximum Ratings ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Theory of Operation Circuit Description Overall Structure Normal Operating Conditions Linear-in-dB Gain Control (VDBS) Inversion of the Gain Slope Gain Magnitude Control (VMAG) Two Classes of Variable Gain Amplifiers Amplitude/Phase Response Noise, Input Capacity, and Dynamic Range Dynamic Range Input Common-Mode Range and Rejection Ratio Output Noise and Peak Swing Offset Compensation Effects of Loading on Gain and AC Response Gain Errors Due to On-Chip Resistor Tolerances Output (Input) Common-Mode Control Using the AD8330 Gain and Swing Adjustments When Loaded Input Coupling DC-Coupled Signal Path Using Single-Sided Sources and Loads Pulse Operation Preserving Absolute Gain Calculation of Noise Figure Noise as a Function of VDBS Distortion Considerations P1dB and V1dB Applications Information ADC Driving Simple AGC Amplifier Wide Range True RMS Voltmeter Evaluation Board General Description Basic Operation Options Measurement Setup AD8330-EVALZ Board Design Outline Dimensions Ordering Guide
011
9 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 9 0
014
100k 1M 10M 100M 500M 0. 0. 0. 0. 0. 0. 0. 0. 0. 1. –0. –0. –0. –0. –0. –0. –0. –0. –0. FREQUENCY (Hz)
03217-
DIFFERENTIAL OFFSET (mV)
03217- Figure 10. Frequency Response for Various Values of VMAG, Figure 13. Differential Input Offset Histogram VDBS = 0.75 V
10 10 VDBS = 0.1V 0 8 B) –10 d ) R ( –20 s RRO Y (n 6 –30 A E L –40 DE ANCE UP 4 AL O –50 B R G UT P –60 UT 2 O –70 –80 0 –90 100k 1M 10M 100M 300M
012
100k 1M 10M 100M
015
FREQUENCY (Hz)
03217-
FREQUENCY (Hz)
03217- Figure 11. Group Delay vs. Frequency Figure 14. Output Balance Error vs. Frequency for a Representative Part
0 200 190 –1 180 V) –2 Ω) 170 T = –40°C ( E (m 160 G –3 A DANCE LT E 150 O P V M T –4 T = +25°C I E 140 UT P OFFS –5 UT 130 O 120 –6 T = +85°C 110 –7 100 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
013
100k M 1 M 0 1 100M 0 3 M 0
016
VDBS (V)
03217-
FREQUENCY (Hz)
03217- Figure 12. Differential Output Offset vs. VDBS for Three Temperatures, Figure 15. Output Impedance vs. Frequency for a Representative Part Rev. G | Page 8 of 32 Document Outline Features Applications Functional Block Diagram General Description Table of Contents Revision History Specifications Absolute Maximum Ratings ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Theory of Operation Circuit Description Overall Structure Normal Operating Conditions Linear-in-dB Gain Control (VDBS) Inversion of the Gain Slope Gain Magnitude Control (VMAG) Two Classes of Variable Gain Amplifiers Amplitude/Phase Response Noise, Input Capacity, and Dynamic Range Dynamic Range Input Common-Mode Range and Rejection Ratio Output Noise and Peak Swing Offset Compensation Effects of Loading on Gain and AC Response Gain Errors Due to On-Chip Resistor Tolerances Output (Input) Common-Mode Control Using the AD8330 Gain and Swing Adjustments When Loaded Input Coupling DC-Coupled Signal Path Using Single-Sided Sources and Loads Pulse Operation Preserving Absolute Gain Calculation of Noise Figure Noise as a Function of VDBS Distortion Considerations P1dB and V1dB Applications Information ADC Driving Simple AGC Amplifier Wide Range True RMS Voltmeter Evaluation Board General Description Basic Operation Options Measurement Setup AD8330-EVALZ Board Design Outline Dimensions Ordering Guide
