Datasheet AD9625 (Analog Devices) - 4
| Manufacturer | Analog Devices |
| Description | 12-Bit, 2.6 GSPS/2.5 GSPS/2.0 GSPS, 1.3 V/2.5 V Analog-to-Digital Converter |
| Pages / Page | 72 / 4 — AD9625. Data Sheet. SPECIFICATIONS DC SPECIFICATIONS. Table 1. Test … |
| Revision | C |
| File Format / Size | PDF / 2.1 Mb |
| Document Language | English |
AD9625. Data Sheet. SPECIFICATIONS DC SPECIFICATIONS. Table 1. Test Conditions/. AD9625-2.0. AD9625-2.5. AD9625-2.6. Parameter. Comments
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AD9625 Data Sheet SPECIFICATIONS DC SPECIFICATIONS
AVDD1 = DVDD1 = DRVDD1 = 1.3 V, AVDD2 = DVDD2 = DRVDD2 = 2.5 V, specified maximum sampling rate, 1.2 V internal reference, AIN = −1.0 dBFS, default SPI settings, dc-coupled output data, unless otherwise noted.
Table 1. Test Conditions/ AD9625-2.0 AD9625-2.5 AD9625-2.6 Parameter Comments Temperature1 Min Typ Max Min Typ Max Min Typ Max Unit
RESOLUTION 12 12 12 Bits ACCURACY No Missing Codes Full Guaranteed Guaranteed Guaranteed Offset Error Full −7 ±0.5 +6.4 −7 ±0.5 +6.4 −8.5 ±0.5 +7.0 LSB Gain Error Full −8 +8 −10.8 +14.2 −13.8 +20.9 %FSR Differential Nonlinearity Full −0.7 ±0.3 +0.7 −0.5 ±0.3 +0.7 −0.6 ±0.3 +0.7 LSB (DNL) Integral Nonlinearity (INL) Full −3.6 ±0.9 +3.6 −2.1 ±1.0 +2.1 −2.7 ±1.0 +2.3 LSB ANALOG INPUTS Differential Input Voltage Range Internal VREF = 1.2 V Full 1.1 1 1 V p-p Resistance 25°C 100 100 100 Ω Capacitance 25°C 1.5 1.5 1.5 pF Internal Common-Mode Full 492 525 563 492 525 563 492 525 563 mV Voltage (VCM) Analog Ful -Power Bandwidth2 Internal termination 25°C 3.2 3.2 3.2 GHz Input Referred Noise 25°C 2 2 2 LSBRMS POWER SUPPLIES AVDD1 Full 1.26 1.3 1.32 1.26 1.3 1.32 1.26 1.3 1.32 V AVDD2 Full 2.4 2.5 2.6 2.4 2.5 2.6 2.4 2.5 2.6 V DRVDD1 Full 1.26 1.3 1.32 1.26 1.3 1.32 1.26 1.3 1.32 V DRVDD2 Full 2.4 2.5 2.6 2.4 2.5 2.6 2.4 2.5 2.6 V DVDD1 Full 1.26 1.3 1.32 1.26 1.3 1.32 1.26 1.3 1.32 V DVDD2 Full 2.4 2.5 2.6 2.4 2.5 2.6 2.4 2.5 2.6 V DVDDIO Full 2.4 2.5 3.3 2.4 2.5 3.3 2.4 2.5 3.3 V SPI_VDDIO Full 2.4 2.5 3.3 2.4 2.5 3.3 2.4 2.5 3.3 V IAVDD1 Full 1120 1222 1250 1351 1267 1390 mA IAVDD2 Full 383 460 427 491 432 492 mA IDRVDD1 Full 456 470 476 518 497 544 mA IDRVDD2 Full 9 10 9 10 9 10 mA IDVDD1 Full 410 430 425 473 441 503 mA IDVDD2 Full <1 <1 <1 mA IDVDDIO Full <1 <1 <1 mA ISPI_VDDIO Full <1 <1 <1 mA Power Dissipation Eight lane mode Full 3.48 3.8 3.90 4.2 4.0 4.3 W Power-Down Dissipation 125 3.8 125 125 mW 1 Full temperature range is −40°C to +85°C measured at the case (TC). 2 See Figure 75 and Figure 76 for networks. Rev. B | Page 4 of 72 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS AD9625-2.0 AD9625-2.5 AD9625-2.6 EQUIVALENT TEST CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE FAST DETECT GAIN THRESHOLD OPERATION Threshold Operation Threshold Format TEST MODES ANALOG INPUT CONSIDERATIONS DIFFERENTIAL INPUT CONFIGURATIONS USING THE ADA4961 DC COUPLING CLOCK INPUT CONSIDERATIONS Clock Jitter Considerations Clock Duty Cycle Considerations DIGITAL DOWNCONVERTERS (DDC) FREQUENCY SYNTHESIZER AND MIXER NUMERICALLY CONTROLLED OSCILLATOR HIGH BANDWIDTH DECIMATOR LOW BANDWIDTH DECIMATOR DIGITAL OUTPUTS INTRODUCTION TO THE JESD204B INTERFACE FUNCTIONAL OVERVIEW Transport Layer Data Link Layer Physical Layer JESD204B LINK ESTABLISHMENT Code Group Synchronization (CGS) and SYNCINB± Initial Lane Alignment Sequence (ILAS) Data Streaming Link Setup Parameters 8-Bit/10-Bit Encoder Digital Outputs, Timing, and Controls De-Emphasis PHYSICAL LAYER OUTPUT SCRAMBLER TAIL BITS DDC MODES (SINGLE AND DUAL) CHECKSUM 8-BIT/10-BIT ENCODER CONTROL INITIAL LANE ALIGNMENT SEQUENCE (ILAS) LANE SYNCHRONIZATION Multichip Synchronization Using SYSREF± Timestamp Six Lane Output Mode ADC Output Control Bits on JESD204B Samples SYSREF± Setup and Hold IRQ IRQ Guardband Delays (SYSREF± Setup and Hold) Using Rising/Falling Edges of the CLK to Latch SYSREF± Test Modes JESD204B APPLICATION LAYERS fS × 2, fS × 4, fS × 8 Modes FRAME ALIGNMENT CHARACTER INSERTION THERMAL CONSIDERATIONS POWER SUPPLY CONSIDERATIONS SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE MEMORY MAP READING THE MEMORY MAP REGISTER Open and Reserved Locations Default Values Logic Levels Transfer Register Map MEMORY MAP REGISTERS APPLICATIONS INFORMATION DESIGN GUIDELINES POWER AND GROUND RECOMMENDATIONS CLOCK STABILITY CONSIDERATIONS SPI PORT OUTLINE DIMENSIONS ORDERING GUIDE
AD9625 Data Sheet SPECIFICATIONS DC SPECIFICATIONS
AVDD1 = DVDD1 = DRVDD1 = 1.3 V, AVDD2 = DVDD2 = DRVDD2 = 2.5 V, specified maximum sampling rate, 1.2 V internal reference, AIN = −1.0 dBFS, default SPI settings, dc-coupled output data, unless otherwise noted.
Table 1. Test Conditions/ AD9625-2.0 AD9625-2.5 AD9625-2.6 Parameter Comments Temperature1 Min Typ Max Min Typ Max Min Typ Max Unit
RESOLUTION 12 12 12 Bits ACCURACY No Missing Codes Full Guaranteed Guaranteed Guaranteed Offset Error Full −7 ±0.5 +6.4 −7 ±0.5 +6.4 −8.5 ±0.5 +7.0 LSB Gain Error Full −8 +8 −10.8 +14.2 −13.8 +20.9 %FSR Differential Nonlinearity Full −0.7 ±0.3 +0.7 −0.5 ±0.3 +0.7 −0.6 ±0.3 +0.7 LSB (DNL) Integral Nonlinearity (INL) Full −3.6 ±0.9 +3.6 −2.1 ±1.0 +2.1 −2.7 ±1.0 +2.3 LSB ANALOG INPUTS Differential Input Voltage Range Internal VREF = 1.2 V Full 1.1 1 1 V p-p Resistance 25°C 100 100 100 Ω Capacitance 25°C 1.5 1.5 1.5 pF Internal Common-Mode Full 492 525 563 492 525 563 492 525 563 mV Voltage (VCM) Analog Ful -Power Bandwidth2 Internal termination 25°C 3.2 3.2 3.2 GHz Input Referred Noise 25°C 2 2 2 LSBRMS POWER SUPPLIES AVDD1 Full 1.26 1.3 1.32 1.26 1.3 1.32 1.26 1.3 1.32 V AVDD2 Full 2.4 2.5 2.6 2.4 2.5 2.6 2.4 2.5 2.6 V DRVDD1 Full 1.26 1.3 1.32 1.26 1.3 1.32 1.26 1.3 1.32 V DRVDD2 Full 2.4 2.5 2.6 2.4 2.5 2.6 2.4 2.5 2.6 V DVDD1 Full 1.26 1.3 1.32 1.26 1.3 1.32 1.26 1.3 1.32 V DVDD2 Full 2.4 2.5 2.6 2.4 2.5 2.6 2.4 2.5 2.6 V DVDDIO Full 2.4 2.5 3.3 2.4 2.5 3.3 2.4 2.5 3.3 V SPI_VDDIO Full 2.4 2.5 3.3 2.4 2.5 3.3 2.4 2.5 3.3 V IAVDD1 Full 1120 1222 1250 1351 1267 1390 mA IAVDD2 Full 383 460 427 491 432 492 mA IDRVDD1 Full 456 470 476 518 497 544 mA IDRVDD2 Full 9 10 9 10 9 10 mA IDVDD1 Full 410 430 425 473 441 503 mA IDVDD2 Full <1 <1 <1 mA IDVDDIO Full <1 <1 <1 mA ISPI_VDDIO Full <1 <1 <1 mA Power Dissipation Eight lane mode Full 3.48 3.8 3.90 4.2 4.0 4.3 W Power-Down Dissipation 125 3.8 125 125 mW 1 Full temperature range is −40°C to +85°C measured at the case (TC). 2 See Figure 75 and Figure 76 for networks. Rev. B | Page 4 of 72 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS AD9625-2.0 AD9625-2.5 AD9625-2.6 EQUIVALENT TEST CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE FAST DETECT GAIN THRESHOLD OPERATION Threshold Operation Threshold Format TEST MODES ANALOG INPUT CONSIDERATIONS DIFFERENTIAL INPUT CONFIGURATIONS USING THE ADA4961 DC COUPLING CLOCK INPUT CONSIDERATIONS Clock Jitter Considerations Clock Duty Cycle Considerations DIGITAL DOWNCONVERTERS (DDC) FREQUENCY SYNTHESIZER AND MIXER NUMERICALLY CONTROLLED OSCILLATOR HIGH BANDWIDTH DECIMATOR LOW BANDWIDTH DECIMATOR DIGITAL OUTPUTS INTRODUCTION TO THE JESD204B INTERFACE FUNCTIONAL OVERVIEW Transport Layer Data Link Layer Physical Layer JESD204B LINK ESTABLISHMENT Code Group Synchronization (CGS) and SYNCINB± Initial Lane Alignment Sequence (ILAS) Data Streaming Link Setup Parameters 8-Bit/10-Bit Encoder Digital Outputs, Timing, and Controls De-Emphasis PHYSICAL LAYER OUTPUT SCRAMBLER TAIL BITS DDC MODES (SINGLE AND DUAL) CHECKSUM 8-BIT/10-BIT ENCODER CONTROL INITIAL LANE ALIGNMENT SEQUENCE (ILAS) LANE SYNCHRONIZATION Multichip Synchronization Using SYSREF± Timestamp Six Lane Output Mode ADC Output Control Bits on JESD204B Samples SYSREF± Setup and Hold IRQ IRQ Guardband Delays (SYSREF± Setup and Hold) Using Rising/Falling Edges of the CLK to Latch SYSREF± Test Modes JESD204B APPLICATION LAYERS fS × 2, fS × 4, fS × 8 Modes FRAME ALIGNMENT CHARACTER INSERTION THERMAL CONSIDERATIONS POWER SUPPLY CONSIDERATIONS SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE MEMORY MAP READING THE MEMORY MAP REGISTER Open and Reserved Locations Default Values Logic Levels Transfer Register Map MEMORY MAP REGISTERS APPLICATIONS INFORMATION DESIGN GUIDELINES POWER AND GROUND RECOMMENDATIONS CLOCK STABILITY CONSIDERATIONS SPI PORT OUTLINE DIMENSIONS ORDERING GUIDE
