Datasheet Texas Instruments ADC10D1000CCMLS
| Manufacturer | Texas Instruments |
| Series | ADC10D1000QML-SP |
| Part Number | ADC10D1000CCMLS |
Datasheets
ADC10D1000QML Low-Power, 10-Bit, Dual 1-GSPS or Single 2-GSPS Analog-to-Digital Converter datasheet
PDF, 1.3 Mb, Revision: G, File published: Dec 7, 2016
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Prices
Status
| Lifecycle Status | Active (Recommended for new designs) |
| Manufacture's Sample Availability | No |
Packaging
| Pin | 376 |
| Package Type | NAA |
| Industry STD Term | CCGA |
| JEDEC Code | S-CBGA-N |
| Package QTY | 1 |
| Device Marking | ADC10D1000CCMLS |
| Width (mm) | 27.94 |
| Length (mm) | 27.94 |
| Thickness (mm) | 2.79 |
| Pitch (mm) | 1.27 |
| Max Height (mm) | 3.5 |
| Mechanical Data | Download |
Parametrics
| # Input Channels | 2,1 |
| Analog Voltage AVDD(Max) | 2.2 V |
| Analog Voltage AVDD(Min) | 1.8 V |
| Architecture | Folding Interpolating |
| ENOB | 9 Bits |
| INL(Max) | 0.7 +/-LSB |
| INL(Typ) | 0.7 +/-LSB |
| Interface | Parallel LVDS |
| Operating Temperature Range | -55 to 125,25 C |
| Package Group | CCGA |
| Package Size: mm2:W x L | 376CCGA: 781 mm2: 27.94 x 27.94(CCGA) PKG |
| Power Consumption(Typ) | 2900 mW |
| Rating | Space |
| Reference Mode | Int |
| Resolution | 10 Bits |
| SFDR | 63 dB |
| SNR | 56.8 dB |
| Sample Rate (max) | 2GSPS SPS |
Eco Plan
| RoHS | See ti.com |
Design Kits & Evaluation Modules
- Evaluation Modules & Boards: ADC-LD-BB
ADC Low Distortion Balun Board
Lifecycle Status: Active (Recommended for new designs) - Evaluation Modules & Boards: ADC10D1000CVAL
10-Bit, Dual 1.0 GSPS / Single 2.0 GSPS Signal Acquisition Evaluation Board
Lifecycle Status: Active (Recommended for new designs) - Evaluation Modules & Boards: ADC12D1600CVAL
ADC12D1600QML-SP 12-Bit, Dual 1.6- or Single 3.2-GSPS, RF-Sampling ADC Evaluation Module - Aerospace
Lifecycle Status: Active (Recommended for new designs) - Evaluation Modules & Boards: ADC-WB-BB
ADC Wide Band Balun Board
Lifecycle Status: Active (Recommended for new designs) - Evaluation Modules & Boards: TC1-DESIQ-SBB
TC1 DESIQ Single Balun Board
Lifecycle Status: Active (Recommended for new designs)
Application Notes
- Signal Chain Noise Figure AnalysisPDF, 615 Kb, File published: Oct 29, 2014
- Synchronizing the Giga-Sample ADCs Interfaced with Multiple FPGAsPDF, 943 Kb, File published: Aug 6, 2014
- AN-2128 ADC1xD1x00 Pin Compatibility (Rev. C)PDF, 60 Kb, Revision: C, File published: May 1, 2013
In order to facilitate upgrading applications from a 10-bit Gig ADC to a 12-bit Gig ADC, the ADC10D1x00(ADC10D1500/ADC10D1000) is designed to be pin-compatible with the ADC12D1x00(ADC12D1800/1600/1000). This means that a single board layout may be designed with both resolutionADCs in mind for more cost efficient and time-to-market product development. - From Sample Instant to Data Output: Understanding Latency in the GSPS ADCPDF, 392 Kb, File published: Dec 18, 2012
For many applications which use ultra high-speed ADCs, latency can be a critical performance specification. For example, if the ADC is used in any kind of feedback loop, then the absolute latency is an important factor. For a MIMO system such as a phased array radar, the relative difference and variability in latency becomes important. This application note covers latency in the GSPS ADC products, - AN-2132 Synchronizing Multiple GSPS ADCs in a System: The AutoSync Feature (Rev. G)PDF, 169 Kb, Revision: G, File published: Feb 3, 2017
Model Line
Series: ADC10D1000QML-SP (2)
- ADC10D1000CCMLS ADC10D1000CCMPR
Manufacturer's Classification
- Semiconductors > Space & High Reliability > Data Converter > Analog to Digital Converters
