Datasheet Texas Instruments SN74S112AD
| Manufacturer | Texas Instruments |
| Series | SN74S112A |
| Part Number | SN74S112AD |
Dual J-K Negative-Edge-Triggered Flip-Flops With Clear And Preset 16-SOIC 0 to 70
Datasheets
Dual J-K Negative-Edge-Triggered Flip-Flops With Preset And Clear datasheet
PDF, 1.3 Mb, File published: Mar 1, 1988
Extract from the document
Status
| Lifecycle Status | Obsolete (Manufacturer has discontinued the production of the device) |
| Manufacture's Sample Availability | No |
Packaging
| Pin | 16 |
| Package Type | D |
| Industry STD Term | SOIC |
| JEDEC Code | R-PDSO-G |
| Width (mm) | 3.91 |
| Length (mm) | 9.9 |
| Thickness (mm) | 1.58 |
| Pitch (mm) | 1.27 |
| Max Height (mm) | 1.75 |
| Mechanical Data | Download |
Parametrics
| Approx. Price (US$) | 0.82 | 1ku |
| Bits(#) | 2 |
| F @ Nom Voltage(Max)(Mhz) | 50 |
| ICC @ Nom Voltage(Max)(mA) | 6 |
| Input Type | TTL |
| Output Drive (IOL/IOH)(Max)(mA) | -1/20 |
| Output Type | TTL |
| Package Group | SOIC |
| Package Size: mm2:W x L (PKG) | See datasheet (PDIP) |
| Rating | Catalog |
| Schmitt Trigger | No |
| Technology Family | S |
| VCC(Max)(V) | 5.25 |
| VCC(Min)(V) | 4.75 |
| Voltage(Nom)(V) | 5 |
| tpd @ Nom Voltage(Max)(ns) | 20 |
Eco Plan
| RoHS | Not Compliant |
| Pb Free | No |
Model Line
Series: SN74S112A (3)
- SN74S112AD SN74S112AN SN74S112AN3
Manufacturer's Classification
- Semiconductors > Logic > Flip-Flop/Latch/Register > J-K Flip-Flop
