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Datasheet Texas Instruments ADS5553IPFP

Datasheet Texas Instruments ADS5553IPFP

ManufacturerTexas Instruments
Part NumberADS5553IPFP

Dual-Channel, 14-Bit, 65-MSPS Analog-to-Digital Converter (ADC) 80-HTQFP -40 to 85


  • Download » Datasheet, PDF, 625 Kb, 02-21-2005
    Dual 14 Bit, 65 MSPS ADC datasheet


Family: ADS5553


Lifecycle StatusActive (Recommended for new designs)
Manufacture's Sample AvailabilityNo


Package TypePFP
Industry STD TermHTQFP
Package QTY96
CarrierJEDEC TRAY (10+1)
Device MarkingADS5553I
Width (mm)12
Length (mm)12
Thickness (mm)1
Pitch (mm).5
Max Height (mm)1.2
Mechanical DataDownload »


# Input Channels2
Analog Input BW750 MHz
DNL(Max)0.6 +/-LSB
DNL(Typ)0.6 +/-LSB
ENOB11.9 Bits
INL(Max)2.5 +/-LSB
INL(Typ)2.5 +/-LSB
Input BufferNo
Input Range2.3 Vp-p
InterfaceParallel CMOS
Operating Temperature Range-40 to 85 C
Package GroupHTQFP
Package Size: mm2:W x L80HTQFP: 196 mm2: 14 x 14(HTQFP) PKG
Power Consumption(Typ)725 mW
Reference ModeExt,Int
Resolution14 Bits
SINAD73.4 dB
SNR74 dB
Sample Rate(Max)65 MSPS

Eco Plan


Design Kits & Evaluation Modules

  • Evaluation Modules & Boards: ADS5553EVM
    ADS5553 Evluation module
    Lifecycle Status: Active (Recommended for new designs)
  • Evaluation Modules & Boards: TSW2200EVM
    TSW2200 Low-Cost Portable Power Supply Evaluation Module
    Lifecycle Status: Active (Recommended for new designs)

Application Notes

  • Download » Application Notes, PDF, 310 Kb, 01-18-2005
    Clocking High-Speed Data Converters
  • Download » Application Notes, PDF, 805 Kb, 09-04-2008
    CDCE62005 as Clock Solution for High-Speed ADCs
    TI has introduced a family of devices well-suited to meet the demands for high-speed ADC devices such as the ADS5527, which is capable of sampling up to 210 MSPS. To realize the full potential of these high-performance products, it is imperative to provide a low phase noise clock source. The CDCE62005 clock synthesizer chip offers a real-world clocking solution to meet these stringent requirements
  • Download » Application Notes, PDF, 2.0 Mb, Revision: A, 05-22-2015
    Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A)
  • Download » Application Notes, PDF, 1.2 Mb, Revision: A, 07-19-2013
    Why Use Oversampling when Undersampling Can Do the Job? (Rev. A)
  • Download » Application Notes, PDF, 376 Kb, 04-28-2009
    Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio
    This application report explains different aspects of selecting analog-to-digital and digital-to-analog data converters for Software-Defined Radio (SDR) applications. It also explains how ADS61xx ADCs and the DAC5688 from Texas Instruments fit properly for SDR designs.
  • Download » Application Notes, PDF, 327 Kb, Revision: A, 09-10-2010
    Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)
    This application report discusses the performance-related aspects of passive and active interfaces at the analog input of high-speed pipeline analog-to-digital converters (ADCs). The report simplifies the many possibilities into two main categories: passive and active interface circuits. The first section of the report gives an overview of equivalent models of buffered and unbuffered ADC input cir
  • Download » Application Notes, PDF, 2.3 Mb, 06-02-2008
    Phase Noise Performance and Jitter Cleaning Ability of CDCE72010
    This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock, VCXO clock, and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig
  • Download » Application Notes, PDF, 424 Kb, 06-08-2008
    CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters
    Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed, high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483, which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices, the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers
  • Download » Application Notes, PDF, 132 Kb, Revision: A, 04-16-2015
    Principles of Data Acquisition and Conversion (Rev. A)
  • Download » Application Notes, PDF, 425 Kb, Revision: B, 10-09-2011
    A Glossary of Analog-to-Digital Specifications and Performance Characteristics (Rev. B)
    This glossary is a collection of the definitions of Texas Instruments' Delta-Sigma (О”ОЈ), successive approximation register (SAR), and pipeline analog-to-digital (A/D) converter specifications and performance characteristics. Although there is a considerable amount of detail in this document, the product data sheet for a particular product specification is the best and final reference.
  • Download » Application Notes, PDF, 69 Kb, Revision: A, 05-18-2015
    Analog-to-Digital Converter Grounding Practices Affect System Performance (Rev. A)

Moldel Line

Series: ADS5553 (2)

Manufacturer's Classification

  • Semiconductors > Data Converters > Analog-to-Digital Converters (ADCs) > High Speed ADCs (>10MSPS)
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