Datasheet Texas Instruments CD74AC08

ManufacturerTexas Instruments
SeriesCD74AC08
Datasheet Texas Instruments CD74AC08

Quad 2-Input AND Gates

Datasheets

Qauadruple 2-Input Positive-AND Gates datasheet
PDF, 982 Kb, Revision: C, File published: Jun 12, 2002
Extract from the document

Prices

Status

CD74AC08ECD74AC08MCD74AC08M96CD74AC08M96E4CD74AC08M96G4CD74AC08MG4
Lifecycle StatusActive (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)
Manufacture's Sample AvailabilityNoNoNoNoNoNo

Packaging

CD74AC08ECD74AC08MCD74AC08M96CD74AC08M96E4CD74AC08M96G4CD74AC08MG4
N123456
Pin141414141414
Package TypeNDDDDD
Industry STD TermPDIPSOICSOICSOICSOICSOIC
JEDEC CodeR-PDIP-TR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-G
Package QTY255025002500250050
CarrierTUBETUBELARGE T&RLARGE T&RLARGE T&RTUBE
Device MarkingCD74AC08EAC08MAC08MAC08MAC08MAC08M
Width (mm)6.353.913.913.913.913.91
Length (mm)19.38.658.658.658.658.65
Thickness (mm)3.91.581.581.581.581.58
Pitch (mm)2.541.271.271.271.271.27
Max Height (mm)5.081.751.751.751.751.75
Mechanical DataDownloadDownloadDownloadDownloadDownloadDownload

Parametrics

Parameters / ModelsCD74AC08E
CD74AC08E
CD74AC08M
CD74AC08M
CD74AC08M96
CD74AC08M96
CD74AC08M96E4
CD74AC08M96E4
CD74AC08M96G4
CD74AC08M96G4
CD74AC08MG4
CD74AC08MG4
Bits444444
ICC @ Nom Voltage(Max), mA0.080.080.080.080.080.08
Operating Temperature Range, C-55 to 125-55 to 125-55 to 125-55 to 125-55 to 125-55 to 125
Output Drive (IOL/IOH)(Max), mA-24/24-24/24-24/24-24/24-24/24-24/24
Package GroupPDIPSOICSOICSOICSOICSOIC
Package Size: mm2:W x L, PKGSee datasheet (PDIP)14SOIC: 52 mm2: 6 x 8.65(SOIC)14SOIC: 52 mm2: 6 x 8.65(SOIC)14SOIC: 52 mm2: 6 x 8.65(SOIC)14SOIC: 52 mm2: 6 x 8.65(SOIC)14SOIC: 52 mm2: 6 x 8.65(SOIC)
RatingCatalogCatalogCatalogCatalogCatalogCatalog
Schmitt TriggerNoNoNoNoNoNo
Technology FamilyACACACACACAC
VCC(Max), V5.55.55.55.55.55.5
VCC(Min), V1.51.51.51.51.51.5
Voltage(Nom), V1.5,3.3,51.5,3.3,51.5,3.3,51.5,3.3,51.5,3.3,51.5,3.3,5
tpd @ Nom Voltage(Max), ns109,12.2,8.7109,12.2,8.7109,12.2,8.7109,12.2,8.7109,12.2,8.7109,12.2,8.7

Eco Plan

CD74AC08ECD74AC08MCD74AC08M96CD74AC08M96E4CD74AC08M96G4CD74AC08MG4
RoHSCompliantCompliantCompliantCompliantCompliantCompliant
Pb FreeYes

Application Notes

  • Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc
    PDF, 43 Kb, File published: Apr 1, 1996
    Though low power consumption is a feature of CMOS devices sometimes this feature does not meet a designer?s system power supply constraints. Therefore a partial system power down or multiple Vcc supplies are used to meet the needs of the system. This document shows electrostatic discharge protection circuits. It also provides circuit and bus driver examples of partial system power down and curren

Model Line

Manufacturer's Classification

  • Semiconductors> Logic> Gate> AND Gate