Datasheet Texas Instruments CDCE906

Manufacturer	Texas Instruments
Series	CDCE906

Datasheets

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Packaging

Parametrics

Parameters / Models	CDCE906PW	CDCE906PWG4	CDCE906PWR	CDCE906PWRG4
Approx. Price (US$)				2.20 | 1ku
Divider Ratio	Universal	Universal	Universal	Universal
Function	Clock Synthesizer,Clock Multiplier,Clock Divider	Clock Synthesizer,Clock Multiplier,Clock Divider	Clock Synthesizer,Clock Multiplier,Clock Divider	Clock Synthesizer Clock Multiplier Clock Divider
Input Level	Crystal,LVCMOS,Differential	Crystal,LVCMOS,Differential	Crystal,LVCMOS,Differential	Crystal LVCMOS Differential
Jitter-Peak to Peak(P-P) or Cycle to Cycle, C-C	60 ps	60 ps	60 ps
Jitter-Peak to Peak(P-P) or Cycle to Cycle(C-C)				60 ps
Operating Temperature Range, C	0 to 70	0 to 70	0 to 70
Operating Temperature Range(C)				0 to 70
Output Frequency(Max), MHz	167	167	167
Output Frequency(Max)(MHz)				167
Output Level	LVCMOS	LVCMOS	LVCMOS	LVCMOS
Output Skew, ps	150	150	150
Output Skew(ps)				150
Package Group	TSSOP	TSSOP	TSSOP	TSSOP
Package Size: mm2:W x L, PKG	20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP)	20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP)	20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP)
Package Size: mm2:W x L (PKG)				20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP)
Rating	Catalog	Catalog	Catalog	Catalog
Special Features	Integrated EEPROM,Multiplier/Divider,Spread Spectrum Clocking (SSC)	Integrated EEPROM,Multiplier/Divider,Spread Spectrum Clocking (SSC)	Integrated EEPROM,Multiplier/Divider,Spread Spectrum Clocking (SSC)	Integrated EEPROM Multiplier/Divider Spread Spectrum Clocking (SSC)
VCC, V	3.3	3.3	3.3
VCC(V)				3.3

Eco Plan

Application Notes

• Download
  Recommended Terminations for the Differential Inputs of CDCE906/CDCE706
  PDF, 84 Kb, File published: Aug 10, 2006
  This application report describes how differential signals (LVDS, LVPECL, and HSTL) can be connected to CDCE706/CDCE906 differential inputs directly. The wide common-mode voltage and smaller swing required make the devices so versatile that they can receive any signal without any complicated coupling and biasing circuits.
• Download
  CDCx706/x906 Termination and Signal Integrity Guidelines (Rev. A)
  PDF, 155 Kb, Revision: A, File published: Nov 28, 2007
  This application report shows and evaluates different schemes for the CDCE706, CDCE906, CDC706, and CDC906. Guidelines for optimizing the series termination are discussed. Additionally, this report describes how the CDCx706/x906 family can be used to drive 1.8-V clock inputs.
• Download
  High Speed Layout Guidelines (Rev. A)
  PDF, 762 Kb, Revision: A, File published: Aug 8, 2017
  Thisapplicationreportaddresseshigh-speedsignals,suchas clocksignalsand theirrouting,and givesdesignersa reviewof the importantcoherences.Withsomesimplerules,electromagneticinterferenceproblemscan be minimizedwithoutusingcomplicatedformulasand expensivesimulationtools.Section1givesa shortintroductionto theory,whileSection
• Download
  Clock Recommendations for the DM643x EVM
  PDF, 121 Kb, File published: Nov 29, 2006
  The DM643x evaluation module (EVM) requires several clock frequencies to run the system properly. The current clocking proposal of the low-cost EVM consists of the VCXO chip PI6CX100-27W, the PLL chip PLL1705, several bus drivers, and a few oscillaors and crystals. This application report discusses several optimized clocking proposals with the Texas Instruments new clock drivers and recommends a m
• Download
  Troubleshooting I2C Bus Protocol
  PDF, 184 Kb, File published: Oct 19, 2009
  When using the I2Cв„ў bus protocol, the designer must ensure that the hardware complies with the I2C standard. This application report describes the I2C protocol and provides guidelines on debugging a missing acknowledgment, selecting the pullup resistors, or meeting the maximum capacitance load of an I2C bus. A conflict occurs if devices sharing the I2C bus have the same slave address. This

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Manufacturer's Classification

• Semiconductors> Clock and Timing> Clock Generators> Spread-Spectrum Clocks