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Datasheet Microchip AT32UC3A3256

ManufacturerMicrochip
SeriesAT32UC3A3256

A complete system-on-chip 32-bit AVR microcontroller

Datasheets

  • Download » Datasheet, PDF, 15.6 Mb, Revision: 10-01-2012
    AT32UC3A3/A4 Series - Complete Datasheet
    Docket ↓
    Features High Performance, Low Power 32-bit Atmel® AVR® Microcontroller – Compact Single-Cycle RISC Instruction Set Including DSP Instruction Set
    – Read-Modify-Write Instructions and Atomic Bit Manipulation
    – Performing up to 1.51DMIPS/MHz Up to 126 DMIPS Running at 84MHz from Flash (1 Wait-State) Up to 63 DMIPS Running at 42MHz from Flash (0 Wait-State)
    – Memory Protection Unit
    Multi-Layer Bus System
    – High-Performance Data Transfers on Separate Buses for Increased Performance
    – 8 Peripheral DMA Channels (PDCA) Improves Speed for Peripheral
    Communication
    – 4 generic DMA Channels for High Bandwidth Data Paths
    Internal High-Speed Flash
    – 256KBytes, 128KBytes, 64KBytes versions
    – Single-Cycle Flash Access up to 36MHz
    – Prefetch Buffer Optimizing Instruction Execution at Maximum Speed
    – 4 ms Page Programming Time and 8ms Full-Chip Erase Time
    – 100,000 Write Cycles, 15-year Data Retention Capability
    – Flash Security Locks and User Defined Configuration Area
    Internal High-Speed SRAM
    – 64KBytes Single-Cycle Access at Full Speed, Connected to CPU Local Bus
    – 64KBytes (2x32KBytes with independent access) on the Multi-Layer Bus System
    Interrupt Controller
    – Autovectored Low Latency Interrupt Service with Programmable Priority
    System Functions
    – Power and Clock Manager Including Internal RC Clock and One 32KHz Oscillator ...
  • Download » Datasheet, PDF, 1.7 Mb, Revision: 10-01-2012
    AT32UC3A3/A4 Series - Summary Datasheet
    Docket ↓
    Features High Performance, Low Power 32-bit Atmel® AVR® Microcontroller – Compact Single-Cycle RISC Instruction Set Including DSP Instruction Set
    – Read-Modify-Write Instructions and Atomic Bit Manipulation
    – Performing up to 1.51DMIPS/MHz Up to 126 DMIPS Running at 84MHz from Flash (1 Wait-State) Up to 63 DMIPS Running at 42MHz from Flash (0 Wait-State)
    – Memory Protection Unit
    Multi-Layer Bus System
    – High-Performance Data Transfers on Separate Buses for Increased Performance
    – 8 Peripheral DMA Channels (PDCA) Improves Speed for Peripheral
    Communication
    – 4 generic DMA Channels for High Bandwidth Data Paths
    Internal High-Speed Flash
    – 256KBytes, 128KBytes, 64KBytes versions
    – Single-Cycle Flash Access up to 36MHz
    – Prefetch Buffer Optimizing Instruction Execution at Maximum Speed
    – 4 ms Page Programming Time and 8ms Full-Chip Erase Time
    – 100,000 Write Cycles, 15-year Data Retention Capability
    – Flash Security Locks and User Defined Configuration Area
    Internal High-Speed SRAM
    – 64KBytes Single-Cycle Access at Full Speed, Connected to CPU Local Bus
    – 64KBytes (2x32KBytes with independent access) on the Multi-Layer Bus System
    Interrupt Controller
    – Autovectored Low Latency Interrupt Service with Programmable Priority
    System Functions
    – Power and Clock Manager Including Internal RC Clock and One 32KHz Oscillator ...
  • Download » Datasheet, PDF, 5.1 Mb, Revision: 04-01-2011
    Atmel AVR 32-bit Architecture Manual - Complete Datasheet
    Docket ↓
    Feature Summary 32-bit load/store RISC architecture
    Up to 15 general-purpose 32-bit registers
    32-bit Stack Pointer, Program Counter, and Link Register reside in register file
    Fully orthogonal instruction set
    Pipelined architecture allows one instruction per clock cycle for most instructions
    Byte, half-word, word and double word memory access
    Fast interrupts and multiple interrupt priority levels
    Optional branch prediction for minimum delay branches
    Privileged and unprivileged modes enabling efficient and secure Operating Systems
    Innovative instruction set together with variable instruction length ensuring industry
    leading code density
    Optional DSP extention with saturated arithmetic, and a wide variety of multiply
    instructions
    Optional extensions for Java, SIMD, Read-Modify-Write to memory, and Coprocessors
    Architectural support for efficient On-Chip Debug solutions
    Optional MPU or MMU allows for advanced operating systems
    FlashVault™ support through Secure State for executing trusted code alongside
    nontrusted code on the same CPU AVR32
    Architecture
    Document 32000D–04/2011 1. Introduction
    AVR32 is a new high-performance 32-bit RISC microprocessor core, designed for cost-sensitive
    embedded applications, with particular emphasis on low power consumption and high code density. In addition, the instruction set architecture has been tuned to allow for a variety of
    microarchitectures, enabling the AVR32 to be implemented as low-, mid-or high-performance ...
  • Download » Datasheet, PDF, 1.1 Mb, Revision: 03-01-2010
    AVR32UC Technical Reference Datasheet
    Docket ↓
    Feature Summary Small area, high clock frequency.
    32-bit load/store AVR32A RISC architecture.
    15 general-purpose 32-bit registers.
    32-bit Stack Pointer, Program Counter and Link Register reside in register file.
    Fully orthogonal instruction set.
    Pipelined architecture allows one instruction per clock cycle for most instructions.
    Byte, half-word, word and double word memory access.
    Fast interrupts and multiple interrupt priority levels.
    Privileged and unprivileged modes enabling efficient and secure Operating Systems.
    Optional MPU allows for operating systems with memory protection.
    Innovative instruction set together with variable instruction length ensuring industry
    leading code density.
    DSP extention with saturating arithmetic, and a wide variety of multiply instructions.
    Memory Read-Modify-Write instructions.
    Optional advanced On-Chip Debug system.
    FlashVault™ support through Secure state for executing trusted code alongside
    nontrusted code on the same CPU.
    Optional floating-point hardware. AVR32UC
    Technical
    Reference
    Manual 32002F–03/2010 AVR32
    1. Introduction
    AVR32 is a new high-performance 32-bit RISC microprocessor core, designed for cost-sensitive ...

Prices

Status

AT32UC3A3256-ALURAT32UC3A3256-ALUTAT32UC3A3256-CTURAT32UC3A3256-CTUTAT32UC3A3256J-CTUR
Lifecycle StatusProduction (Appropriate for new designs but newer alternatives may exist)Production (Appropriate for new designs but newer alternatives may exist)Production (Appropriate for new designs but newer alternatives may exist)Production (Appropriate for new designs but newer alternatives may exist)Production (Appropriate for new designs but newer alternatives may exist)

Packaging

Parametrics

AT32UC3A3256-ALURAT32UC3A3256-ALUTAT32UC3A3256-CTURAT32UC3A3256-CTUTAT32UC3A3256J-CTUR
ADCC with ComputationNoNoNoNoNo
Angular TimerNoNoNoNoNo
Architecture3232323232
CPU32-bit AVR32-bit AVR32-bit AVR32-bit AVR32-bit AVR
CRC/ScanNoNoNoNoNo
Cap. Touch Channels3232323232
High Voltage CapableNoNoNoNoNo
I2C22222
Internal Oscillator115Khz115Khz115Khz115Khz115Khz
Internal Voltage Reference, BandgapYesYesYesYesYes
Math AcceleratorNoNoNoNoNo
Max # PWM outputs, including complementary outputs1212121212
Max 16 Bit Digital Timers66666
Max A/D Resolution, bits1010101010
Max D/A Resolution, bits1616161616
Max. CPU Speed MHz8484848484
Number of D/A Converters11111
Number of USB Modules11111
Operating Temperature Range, °C-40 to +85-40 to +85-40 to +85-40 to +85
Operation Voltage Max.(V)3.63.63.63.63.6
Operation Voltage Min.(V)33333
Peripheral Pin Select, PPSYesYesYesYesYes
Pin count144144144144144
Program Memory Size, Kbytes256256256256256
RAM, bytes131072131072131072131072131072
SPI™66666
Temp. Range Max.8585858585
Temp. Range Min.-40-40-40-40-40
Total # of A/D channels88888
UART44444
Windowed Watchdog Timer, WWDTNoNoNoNoNo
Zero Cross detectNoNoNoNoNo

Eco Plan

Other Options

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Moldel Line

Series: AT32UC3A3256 (5)

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