Datasheet LAPIS Semiconductor MR48V256C
The MR48V256C is a nonvolatile 32,768-word x 8-bit ferroelectric random access memory (FeRAM) fabricated in silicon-gate CMOS technology.
As FeRAM cells are nonvolatile, backup batteries to hold data can be eliminated.
And, data can be read and written like SRAM, no erase or block operation is needed.
The device is guaranteed for the write/read tolerance of 1012 cycles per bit and the rewrite count can be extended significantly.
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Issue Date: Nov. 13, 2013 MR48V256C
32,768-Word п‚ґ 8-Bit FeRAM (Ferroelectric Random Access Memory) GENERAL DESCRIPTION
The MR48V256C is a nonvolatile 32,768-word x 8-bit ferroelectric random access memory (FeRAM) developed
in the ferroelectric process and silicon-gate CMOS technology. Unlike SRAMs, this device, whose cells are
nonvolatile, eliminates battery backup required to hold data. This device has no mechanisms of erasing and
programming memory cells and blocks, such as those used for various EEPROMs. Therefore, the write cycle
time can be equal to the read cycle time and the power consumption during a write can be reduced significantly.
The MR48V256C can be used in various applications, because the device is guaranteed for the write/read
tolerance of 1012 cycles per bit and the rewrite count can be extended significantly. FEATURES 32,768-word п‚ґ 8-bit configuration
A single 2.7 to 3.6V power supply
Read access time:
70 ns (Max.)
Write enable time:
70 ns (Min.)
Random read/write cycle time
150 ns (Min.)
Guaranteed operating temperature range
пЂ40 to 85п‚°C (Extended temperature version) ...
|Data Retention||10 years|
|Operating Temperature(°C)||-40 to +85|
|Read/Write Endurance||1012 Times|