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Datasheet Texas Instruments OPA820ID

Datasheet Texas Instruments OPA820ID

ManufacturerTexas Instruments
SeriesOPA820
Part NumberOPA820ID

Unity Gain Stable,Low Noise,Voltage Feedback Operational Amplifier 8-SOIC -40 to 85

Datasheets

  • Download » Datasheet, PDF, 1.6 Mb, Revision: D, 12-12-2016
    OPA820 Unity-Gain Stable, Low-Noise, Voltage-Feedback Operational Amplifier datasheet
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    Documents OPA820
    SBOS303D – JUNE 2004 – REVISED DECEMBER 2016 OPA820 Unity-Gain Stable, Low-Noise, Voltage-Feedback Operational Amplifier
    1 Features 3 Description The OPA820 device provides a wideband, unity-gain
    stable, voltage-feedback amplifier with a very-low
    input-noise voltage and high-output current using a
    low 5.6-mA supply current. At unity-gain, the OPA820
    device gives more than 800-MHz bandwidth with less
    than 1-dB peaking. The OPA820 device complements
    this high-speed operation with excellent DC precision
    in a low-power device. A worst-case input-offset
    voltage of ±750 µV and an offset current of ±400 nA
    provide excellent absolute DC precision for pulse
    amplifier applications. 1 High Bandwidth (240 MHz, G = 2)
    High-Output Current (±110 mA)
    Low-Input Noise (2.5 nV/√Hz)
    Low-Supply Current (5.6 mA)
    Flexible Supply Voltage:
    – Dual ±2.5 V to ±6 V ...

Prices

Family: OPA820

Status

Lifecycle StatusActive (Recommended for new designs)
Manufacture's Sample AvailabilityYes

Packaging

Pin88
Package TypeDD
Industry STD TermSOICSOIC
JEDEC CodeR-PDSO-GR-PDSO-G
Package QTY7575
CarrierTUBETUBE
Device MarkingOPA820
Width (mm)3.913.91
Length (mm)4.94.9
Thickness (mm)1.581.58
Pitch (mm)1.271.27
Max Height (mm)1.751.75
Mechanical DataDownload »Download »

Parametrics

2nd Harmonic85 dBc
3rd Harmonic95 dBc
@ MHz1
Acl, min spec gain1 V/V
Additional FeaturesN/A
ArchitectureBipolar,Voltage FB
BW @ Acl800 MHz
CMRR(Min)76 dB
CMRR(Typ)85 dB
GBW(Typ)800 MHz
Input Bias Current(Max)16000000 pA
Iq per channel(Max)5.75 mA
Iq per channel(Typ)5.6 mA
Number of Channels1
Offset Drift(Typ)4 uV/C
Operating Temperature Range-40 to 85 C
Output Current(Typ)110 mA
Package GroupSOIC
Package Size: mm2:W x L8SOIC: 29 mm2: 6 x 4.9(SOIC) PKG
Rail-to-RailNo
RatingCatalog
Slew Rate(Typ)240 V/us
Total Supply Voltage(Max)12 +5V=5, +/-5V=10
Total Supply Voltage(Min)5 +5V=5, +/-5V=10
Vn at 1kHz(Typ)2.5 nV/rtHz
Vn at Flatband(Typ)2.5 nV/rtHz
Vos (Offset Voltage @ 25C)(Max)1.1 mV

Eco Plan

RoHSCompliant

Design Kits & Evaluation Modules

  • Evaluation Modules & Boards: DEM-OPA-SOT-1A
    Unpopulated PCB Compatible w/High Speed, Wide Bandwidth Op Amps in SOT(DBV) Pkg
    Lifecycle Status: Active (Recommended for new designs)
  • Evaluation Modules & Boards: DEM-OPA-SO-1A
    DEM-OPA-SO-1A Unpopulated PCB Compatible w/High Speed Wide Bandwidth Op Amps in 8-lead SOIC (D) Pkg
    Lifecycle Status: Active (Recommended for new designs)

Application Notes

  • Download » Application Notes, PDF, 299 Kb, Revision: A, 05-13-2015
    RLC Filter Design for ADC Interface Applications (Rev. A)
    As high performance Analog-to-Digital Converters (ADCs) continue to improve in their performance, the last stage interface from the final amplifier into the converter inputs becomes a critical element in the system design if the full converter dynamic range is desired. This application note describes the performance and design equations for a simple passive 2nd-order filter used successfully in AD
  • Download » Application Notes, PDF, 273 Kb, 04-22-2004
    ADS5500, OPA695: PC Board Layout for Low Distortion High-Speed ADC Drivers
    Once an analog-to-digital converter (ADC) and a driver/interface have been selected for a given application, the next step to achieving excellent performance is laying out the printed circuit board (PCB) that will support the application. This application report describes several techniques for optimizing a high-speed, 14-bit performance, differential driver PCB layout using a wideband operation
  • Download » Application Notes, PDF, 597 Kb, 06-21-2005
    Wideband Complementary Current Output DAC Single-Ended Interface
    High-speed digital-to-analog converters (DACs) most often use a transformer-coupled output stage. In applications where this configuration is not practical, a single op ampdifferential to single-ended stage has often been used. This application note steps through the exact design equations required to achieve gain matching from each output as well as a matched input impedance to each of the DA
  • Download » Application Notes, PDF, 134 Kb, 07-07-2003
    Measuring Board Parasitics in High-Speed Analog Design
    Successful circuit designs using high-speed amplifiers can depend upon understanding and identifying parasitic PCB components. Simulating a design while including PCB parasitics can protect against unpleasant production surprises. This application report discusses an easy method for measuring parasitic components in a prototype or final PC board design by using a standard oscilloscope and low freq
  • Download » Application Notes, PDF, 256 Kb, Revision: A, 01-17-2005
    Noise Analysis for High Speed Op Amps (Rev. A)
    As system bandwidths have increased an accurate estimate of the noise contribution for each element in the signal channel has become increasingly important. Many designers are not however particularly comfortable with the calculations required to predict the total noise for an op amp or in the conversions between the different descriptions of noise. Considerable inconsistency between manufactu

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Series: OPA820 (9)

Manufacturer's Classification

  • Semiconductors > Amplifiers > Operational Amplifiers (Op Amps) > High-Speed Op Amps (>=50MHz)
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