Datasheet Texas Instruments SN65LVDS104PW

ManufacturerTexas Instruments
SeriesSN65LVDS104
Part NumberSN65LVDS104PW
Datasheet Texas Instruments SN65LVDS104PW

1:4 LVDS Clock Fanout Buffer 16-TSSOP -40 to 85

Datasheets

SN65LVDS10x 4-Port LVDS and 4-Port TTL-to-LVDS Repeaters datasheet
PDF, 1.2 Mb, Revision: G, File published: Dec 31, 2015
Extract from the document

Prices

Status

Lifecycle StatusActive (Recommended for new designs)
Manufacture's Sample AvailabilityYes

Packaging

Pin16
Package TypePW
Industry STD TermTSSOP
JEDEC CodeR-PDSO-G
Package QTY90
CarrierTUBE
Device MarkingLVDS104
Width (mm)4.4
Length (mm)5
Thickness (mm)1
Pitch (mm).65
Max Height (mm)1.2
Mechanical DataDownload

Parametrics

Input Frequency(Max)400 MHz
Input LevelLVDS
Number of Outputs4
Operating Temperature Range-40 to 85 C
Output Frequency(Max)400 MHz
Output LevelLVDS
Package GroupTSSOP
Package Size: mm2:W x L16TSSOP: 32 mm2: 6.4 x 5(TSSOP) PKG
RatingCatalog
VCC3.3 V
VCC Out3.3 V

Eco Plan

RoHSCompliant

Application Notes

  • DC-Coupling Between Differential LVPECL, LVDS, HSTL, and CML
    PDF, 135 Kb, File published: Feb 19, 2003
  • AC Coupling Between Differential LVPECL, LVDS, HSTL and CML (Rev. C)
    PDF, 417 Kb, Revision: C, File published: Oct 17, 2007
    This report provides a quick reference of ac-coupling techniques for interfacing between different logic levels. The four differential signaling levels found in this reportare low-voltage positive-referenced emitter coupled logic (LVPECL), low-voltage differential signals (LVDS), high-speed transceiver logic (HSTL), and current-modelogic (CML). From these four differential signaling levels, 16

Model Line

Manufacturer's Classification

  • Semiconductors > Clock and Timing > Clock Buffers > Differential