Datasheet MCP601, MCP601R, MCP602, MCP603, MCP604 (Microchip) - 14

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MCP601/1R/2/3/4 4.6 Unused Op Amps
2. Connect the guard ring to the non-inverting input pin (VIN+) for inverting gain amplifiers and An unused op amp in a quad package (MCP604) transimpedance amplifiers (converts current to should be configured as shown in Figure 4-6. These voltage, such as photo detectors). This biases circuits prevent the output from toggling and causing the guard ring to the same reference voltage as crosstalk. Circuits A sets the op amp at its minimum the op amp (e.g., VDD/2 or ground). noise gain. The resistor divider produces any desired reference voltage within the output voltage range of the
4.8 Typical Applications
op amp; the op amp buffers that reference voltage. Circuit B uses the minimum number of components 4.8.1 ANALOG FILTERS and operates as a comparator, but it may draw more current. Figure 4-8 and Figure 4-9 show low-pass, second- order, Butterworth filters with a cutoff frequency of 10 Hz. The filter in Figure 4-8 has a non-inverting gain
¼ MCP604 (A) ¼ MCP604 (B)
of +1 V/V, and the filter in Figure 4-9 has an inverting VDD VDD gain of -1 V/V. VDD R1 C G = +1 V/V 1 f V 47 nF P = 10 Hz R REF 2 R1 R2 382 kΩ 641 kΩ R2 V V = V ⋅ --------- IN + REF DD R + R 1 2 C2
MCP60X
VOUT 22 nF
FIGURE 4-6:
Unused Op Amps. –
4.7 PCB Surface Leakage FIGURE 4-8:
Second-Order, Low-Pass In applications where low input bias current is critical, Sallen-Key Filter. printed circuit board (PCB) surface leakage effects need to be considered. Surface leakage is caused by humidity, dust or other contamination on the board. R G = -1 V/V 2 Under low humidity conditions, a typical resistance fP = 10 Hz 618 kΩ between nearby traces is 1012Ω. A 5V difference would cause 5 pA of current to flow. This is greater than the MCP601/1R/2/3/4 family’s bias current at R1 R3 C1 +25°C (1 pA, typical). 618 kΩ 1.00 MΩ 8.2 nF The easiest way to reduce surface leakage is to use a V V IN OUT guard ring around sensitive pins (or traces). The guard C2 – ring is biased at the same voltage as the sensitive pin. 47 nF An example of this type of layout is shown in
MCP60X
Figure 4-7. VDD/2 + Guard Ring VIN– VIN+
FIGURE 4-9:
Second-Order, Low-Pass Multiple-Feedback Filter. The MCP601/1R/2/3/4 family of op amps have low input bias current, which allows the designer to select larger resistor values and smaller capacitor values for these filters. This helps produce a compact PCB layout.
FIGURE 4-7:
Example Guard Ring layout. These filters, and others, can be designed using Microchip’s Design Aids; see
Section 5.2 “FilterLab®
1. Connect the guard ring to the inverting input pin
Software”
and
Section 5.3 “Mindi™ Simulatior
(VIN–) for non-inverting gain amplifiers, includ-
Tool”
. ing unity-gain buffers. This biases the guard ring to the common mode input voltage. DS21314G-page 14 © 2007 Microchip Technology Inc. Document Outline 1.0 Electrical Characteristics FIGURE 1-1: MCP603 Chip Select (CS) Timing Diagram. 1.1 Test Circuits FIGURE 1-2: AC and DC Test Circuit for Most Non-Inverting Gain Conditions. FIGURE 1-3: AC and DC Test Circuit for Most Inverting Gain Conditions. 2.0 Typical Performance Curves FIGURE 2-1: Open-Loop Gain, Phase vs. Frequency. FIGURE 2-2: Slew Rate vs. Temperature. FIGURE 2-3: Gain Bandwidth Product, Phase Margin vs. Temperature. FIGURE 2-4: Quiescent Current vs. Supply Voltage. FIGURE 2-5: Quiescent Current vs. Temperature. FIGURE 2-6: Input Noise Voltage Density vs. Frequency. FIGURE 2-7: Input Offset Voltage. FIGURE 2-8: Input Offset Voltage vs. Temperature. FIGURE 2-9: Input Offset Voltage vs. Common Mode Input Voltage with VDD = 2.7V. FIGURE 2-10: Input Offset Voltage Drift. FIGURE 2-11: CMRR, PSRR vs. Temperature. FIGURE 2-12: Input Offset Voltage vs. Common Mode Input Voltage with VDD = 5.5V. FIGURE 2-13: Channel-to-Channel Separation vs. Frequency. FIGURE 2-14: Input Bias Current, Input Offset Current vs. Ambient Temperature. FIGURE 2-15: DC Open-Loop Gain vs. Load Resistance. FIGURE 2-16: CMRR, PSRR vs. Frequency. FIGURE 2-17: Input Bias Current, Input Offset Current vs. Common Mode Input Voltage. FIGURE 2-18: DC Open-Loop Gain vs. Supply Voltage. FIGURE 2-19: Gain Bandwidth Product, Phase Margin vs. Load Resistance. FIGURE 2-20: Output Voltage Headroom vs. Output Current. FIGURE 2-21: Maximum Output Voltage Swing vs. Frequency. FIGURE 2-22: DC Open-Loop Gain vs. Temperature. FIGURE 2-23: Output Voltage Headroom vs. Temperature. FIGURE 2-24: Output Short-Circuit Current vs. Supply Voltage. FIGURE 2-25: Large Signal Non-Inverting Pulse Response. FIGURE 2-26: Small Signal Non-Inverting Pulse Response. FIGURE 2-27: Chip Select Timing (MCP603). FIGURE 2-28: Large Signal Inverting Pulse Response. FIGURE 2-29: Small Signal Inverting Pulse Response. FIGURE 2-30: Quiescent Current Through VSS vs. Chip Select Voltage (MCP603). FIGURE 2-31: Chip Select Pin Input Current vs. Chip Select Voltage. FIGURE 2-32: Hysteresis of Chip Select’s Internal Switch. FIGURE 2-33: The MCP601/1R/2/3/4 family of op amps shows no phase reversal under input overdrive. FIGURE 2-34: Measured Input Current vs. Input Voltage (below VSS). 3.0 Pin Descriptions TABLE 3-1: Pin Function Table For Single Op Amps TABLE 3-2: Pin Function Table For Dual And Quad Op Amps 3.1 Analog Outputs 3.2 Analog Inputs 3.3 Chip Select Digital Input 3.4 Power Supply Pins 4.0 Applications Information 4.1 Inputs FIGURE 4-1: Simplified Analog Input ESD Structures. FIGURE 4-2: Protecting the Analog Inputs. FIGURE 4-3: Unity Gain Buffer has a Limited VOUT Range. 4.2 Rail-to-Rail Output 4.3 MCP603 Chip Select 4.4 Capacitive Loads FIGURE 4-4: Output resistor RISO stabilizes large capacitive loads. FIGURE 4-5: Recommended RISO values for capacitive loads. 4.5 Supply Bypass 4.6 Unused Op Amps FIGURE 4-6: Unused Op Amps. 4.7 PCB Surface Leakage FIGURE 4-7: Example Guard Ring layout. 4.8 Typical Applications FIGURE 4-8: Second-Order, Low-Pass Sallen-Key Filter. FIGURE 4-9: Second-Order, Low-Pass Multiple-Feedback Filter. FIGURE 4-10: Three-Op Amp Instrumentation Amplifier. FIGURE 4-11: Two-Op Amp Instrumentation Amplifier. FIGURE 4-12: Photovoltaic Mode Detector. FIGURE 4-13: Photoconductive Mode Detector. 5.0 Design Aids 5.1 SPICE Macro Model 5.2 FilterLab® Software 5.3 Mindi™ Simulatior Tool 5.4 MAPS (Microchip Advanced Part Selector) 5.5 Analog Demonstration and Evaluation Boards 5.6 Application Notes 6.0 Packaging Information 6.1 Package Marking Information