Datasheet LTC2293, LTC2292, LTC2291 (Analog Devices) - 21
| Manufacturer | Analog Devices |
| Description | Dual 12-Bit, 65Msps Low Power 3V ADCs |
| Pages / Page | 28 / 21 — APPLICATIO S I FOR ATIO. Maximum and Minimum Conversion Rates. Table 1. … |
| File Format / Size | PDF / 1.1 Mb |
| Document Language | English |
APPLICATIO S I FOR ATIO. Maximum and Minimum Conversion Rates. Table 1. Output Codes vs Input Voltage. A + – A –. D11 – D0
Model Line for this Datasheet
- LTC2291CUP#PBF LTC2291CUP#PBF LTC2291CUP#TRPBF LTC2291CUP#TRPBF LTC2291IUP#PBF LTC2291IUP#PBF LTC2291IUP#TRPBF LTC2291IUP#TRPBF
Text Version of Document
LTC2293/LTC2292/LTC2291
U U W U APPLICATIO S I FOR ATIO Maximum and Minimum Conversion Rates Table 1. Output Codes vs Input Voltage A + – A – D11 – D0 D11 – D0
The maximum conversion rate for the LTC2293/LTC2292/
IN IN (2V Range) OF (Offset Binary) (2’s Complement)
LTC2291 is 65Msps (LTC2293), 40Msps (LTC2292), and >+1.000000V 1 1111 1111 1111 0111 1111 1111 25Msps (LTC2291). For the ADC to operate properly, the +0.999512V 0 1111 1111 1111 0111 1111 1111 CLK signal should have a 50% (±5%) duty cycle. Each half +0.999024V 0 1111 1111 1110 0111 1111 1110 cycle must have at least 7.3ns (LTC2293), 11.8ns +0.000488V 0 1000 0000 0001 0000 0000 0001 (LTC2292), and 18.9ns (LTC2291) for the ADC internal 0.000000V 0 1000 0000 0000 0000 0000 0000 circuitry to have enough settling time for proper operation. –0.000488V 0 0111 1111 1111 1111 1111 1111 –0.000976V 0 0111 1111 1110 1111 1111 1110 An optional clock duty cycle stabilizer circuit can be used –0.999512V 0 0000 0000 0001 1000 0000 0001 if the input clock has a non 50% duty cycle. This circuit –1.000000V 0 0000 0000 0000 1000 0000 0000 <–1.000000V 1 0000 0000 0000 1000 0000 0000 uses the rising edge of the CLK pin to sample the analog input. The falling edge of CLK is ignored and the internal falling edge is generated by a phase-locked loop. The
Digital Output Buffers
input clock duty cycle can vary from 40% to 60% and the Figure 14 shows an equivalent circuit for a single output clock duty cycle stabilizer will maintain a constant 50% buffer. Each buffer is powered by OVDD and OGND, iso- internal duty cycle. If the clock is turned off for a long lated from the ADC power and ground. The additional period of time, the duty cycle stabilizer circuit will require N-channel transistor in the output driver allows operation a hundred clock cycles for the PLL to lock onto the input down to low voltages. The internal resistor in series with clock. To use the clock duty cycle stabilizer, the MODE pin the output makes the output appear as 50Ω to external should be connected to 1/3VDD or 2/3VDD using external circuitry and may eliminate the need for external damping resistors. The MODE pin controls both Channel A and resistors. Channel B—the duty cycle stabilizer is either on or off for both channels. LTC2293/LTC2292/LTC2291 OVDD The lower limit of the LTC2293/LTC2292/LTC2291 sample 0.5V V TO 3.6V DD VDD rate is determined by droop of the sample-and-hold cir- 0.1µF cuits. The pipelined architecture of this ADC relies on OV storing analog signals on small valued capacitors. Junc- DD tion leakage will discharge the capacitors. The specified DATA PREDRIVER 43Ω TYPICAL FROM LOGIC DATA minimum operating frequency for the LTC2293/LTC2292/ LATCH OUTPUT LTC2291 is 1Msps. OE OGND
DIGITAL OUTPUTS
229321 F14 Table 1 shows the relationship between the analog input
Figure 14. Digital Output Buffer
voltage, the digital data bits and the overflow bit. As with all high speed/high resolution converters, the digi- tal output loading can affect the performance. The digital outputs of the LTC2293/LTC2292/LTC2291 should drive a minimal capacitive load to avoid possible interaction between the digital outputs and sensitive input circuitry. The output should be buffered with a device such as an 229321fa 21
U U W U APPLICATIO S I FOR ATIO Maximum and Minimum Conversion Rates Table 1. Output Codes vs Input Voltage A + – A – D11 – D0 D11 – D0
The maximum conversion rate for the LTC2293/LTC2292/
IN IN (2V Range) OF (Offset Binary) (2’s Complement)
LTC2291 is 65Msps (LTC2293), 40Msps (LTC2292), and >+1.000000V 1 1111 1111 1111 0111 1111 1111 25Msps (LTC2291). For the ADC to operate properly, the +0.999512V 0 1111 1111 1111 0111 1111 1111 CLK signal should have a 50% (±5%) duty cycle. Each half +0.999024V 0 1111 1111 1110 0111 1111 1110 cycle must have at least 7.3ns (LTC2293), 11.8ns +0.000488V 0 1000 0000 0001 0000 0000 0001 (LTC2292), and 18.9ns (LTC2291) for the ADC internal 0.000000V 0 1000 0000 0000 0000 0000 0000 circuitry to have enough settling time for proper operation. –0.000488V 0 0111 1111 1111 1111 1111 1111 –0.000976V 0 0111 1111 1110 1111 1111 1110 An optional clock duty cycle stabilizer circuit can be used –0.999512V 0 0000 0000 0001 1000 0000 0001 if the input clock has a non 50% duty cycle. This circuit –1.000000V 0 0000 0000 0000 1000 0000 0000 <–1.000000V 1 0000 0000 0000 1000 0000 0000 uses the rising edge of the CLK pin to sample the analog input. The falling edge of CLK is ignored and the internal falling edge is generated by a phase-locked loop. The
Digital Output Buffers
input clock duty cycle can vary from 40% to 60% and the Figure 14 shows an equivalent circuit for a single output clock duty cycle stabilizer will maintain a constant 50% buffer. Each buffer is powered by OVDD and OGND, iso- internal duty cycle. If the clock is turned off for a long lated from the ADC power and ground. The additional period of time, the duty cycle stabilizer circuit will require N-channel transistor in the output driver allows operation a hundred clock cycles for the PLL to lock onto the input down to low voltages. The internal resistor in series with clock. To use the clock duty cycle stabilizer, the MODE pin the output makes the output appear as 50Ω to external should be connected to 1/3VDD or 2/3VDD using external circuitry and may eliminate the need for external damping resistors. The MODE pin controls both Channel A and resistors. Channel B—the duty cycle stabilizer is either on or off for both channels. LTC2293/LTC2292/LTC2291 OVDD The lower limit of the LTC2293/LTC2292/LTC2291 sample 0.5V V TO 3.6V DD VDD rate is determined by droop of the sample-and-hold cir- 0.1µF cuits. The pipelined architecture of this ADC relies on OV storing analog signals on small valued capacitors. Junc- DD tion leakage will discharge the capacitors. The specified DATA PREDRIVER 43Ω TYPICAL FROM LOGIC DATA minimum operating frequency for the LTC2293/LTC2292/ LATCH OUTPUT LTC2291 is 1Msps. OE OGND
DIGITAL OUTPUTS
229321 F14 Table 1 shows the relationship between the analog input
Figure 14. Digital Output Buffer
voltage, the digital data bits and the overflow bit. As with all high speed/high resolution converters, the digi- tal output loading can affect the performance. The digital outputs of the LTC2293/LTC2292/LTC2291 should drive a minimal capacitive load to avoid possible interaction between the digital outputs and sensitive input circuitry. The output should be buffered with a device such as an 229321fa 21
