Datasheet LT3013B (Analog Devices) - 9
| Manufacturer | Analog Devices |
| Description | 250mA, 4V to 80V Low Dropout Micropower Linear Regulator with PWRGD |
| Pages / Page | 16 / 9 — APPLICATIONS INFORMATION. PWRGD Flag and Timing Capacitor Delay. Figure … |
| File Format / Size | PDF / 178 Kb |
| Document Language | English |
APPLICATIONS INFORMATION. PWRGD Flag and Timing Capacitor Delay. Figure 2. Ceramic Capacitor DC Bias Characteristics
Model Line for this Datasheet
Text Version of Document
LT3013B
APPLICATIONS INFORMATION
and temperature coeffi cients as shown in Figures 2 and 3. only specify operating temperature range and maximum When used with a 5V regulator, a 16V 10μF Y5V capacitor capacitance change over temperature. Capacitance change can exhibit an effective value as low as 1μF to 2μF for the due to DC bias with X5R and X7R capacitors is better than DC bias voltage applied and over the operating tempera- Y5V and Z5U capacitors, but can still be signifi cant enough ture range. The X5R and X7R dielectrics result in more to drop capacitor values below appropriate levels. Capaci- stable characteristics and are more suitable for use as the tor DC bias characteristics tend to improve as component output capacitor. The X7R type has better stability across case size increases, but expected capacitance at operating temperature, while the X5R is less expensive and is avail- voltage should be verifi ed. able in higher values. Care still must be exercised when Voltage and temperature coeffi cients are not the only using X5R and X7R capacitors; the X5R and X7R codes sources of problems. Some ceramic capacitors have a piezoelectric response. A piezoelectric device generates 20 BOTH CAPACITORS ARE 16V, voltage across its terminals due to mechanical stress, simi- 1210 CASE SIZE, 10μF 0 lar to the way a piezoelectric accelerometer or microphone X5R works. For a ceramic capacitor the stress can be induced –20 by vibrations in the system or thermal transients. –40
PWRGD Flag and Timing Capacitor Delay
–60 CHANGE IN VALUE (%) The PWRGD fl ag is used to indicate that the ADJ pin volt- Y5V –80 age is within 10% of the regulated voltage. The PWRGD pin is an open-collector output, capable of sinking 50μA –100 0 2 4 6 8 10 12 14 16 of current when the ADJ pin voltage is low. There is no DC BIAS VOLTAGE (V) internal pull-up on the PWRGD pin; an external pull-up 3013 F02 resistor must be used. When the ADJ pin rises to within
Figure 2. Ceramic Capacitor DC Bias Characteristics
10% of its fi nal reference value, a delay timer is started. At the end of this delay, programmed by the value of the 40 capacitor on the CT pin, the PWRGD pin switches to a high impedance and is pulled up to a logic level by an external 20 pull-up resistor. 0 X5R To calculate the capacitor value on the CT pin, use the –20 following formula: –40 Y5V I t C CT DELAY –60 TIME = • CHANGE IN VALUE (%) V – V CT HIGH ( ) CT LOW ( ) –80 BOTH CAPACITORS ARE 16V, Figure 4 shows a block diagram of the PWRGD circuit. At 1210 CASE SIZE, 10μF –100 –50 –25 0 25 50 75 100 125 start-up, the timing capacitor is discharged and the PWRGD TEMPERATURE (°C) pin will be held low. As the output voltage increases and 3013 F03 the ADJ pin crosses the 90% threshold, the JK fl ip-fl op
Figure 3. Ceramic Capacitor Temperature Characteristics
is reset, and the 3μA current source begins to charge the 3013bfb 9
APPLICATIONS INFORMATION
and temperature coeffi cients as shown in Figures 2 and 3. only specify operating temperature range and maximum When used with a 5V regulator, a 16V 10μF Y5V capacitor capacitance change over temperature. Capacitance change can exhibit an effective value as low as 1μF to 2μF for the due to DC bias with X5R and X7R capacitors is better than DC bias voltage applied and over the operating tempera- Y5V and Z5U capacitors, but can still be signifi cant enough ture range. The X5R and X7R dielectrics result in more to drop capacitor values below appropriate levels. Capaci- stable characteristics and are more suitable for use as the tor DC bias characteristics tend to improve as component output capacitor. The X7R type has better stability across case size increases, but expected capacitance at operating temperature, while the X5R is less expensive and is avail- voltage should be verifi ed. able in higher values. Care still must be exercised when Voltage and temperature coeffi cients are not the only using X5R and X7R capacitors; the X5R and X7R codes sources of problems. Some ceramic capacitors have a piezoelectric response. A piezoelectric device generates 20 BOTH CAPACITORS ARE 16V, voltage across its terminals due to mechanical stress, simi- 1210 CASE SIZE, 10μF 0 lar to the way a piezoelectric accelerometer or microphone X5R works. For a ceramic capacitor the stress can be induced –20 by vibrations in the system or thermal transients. –40
PWRGD Flag and Timing Capacitor Delay
–60 CHANGE IN VALUE (%) The PWRGD fl ag is used to indicate that the ADJ pin volt- Y5V –80 age is within 10% of the regulated voltage. The PWRGD pin is an open-collector output, capable of sinking 50μA –100 0 2 4 6 8 10 12 14 16 of current when the ADJ pin voltage is low. There is no DC BIAS VOLTAGE (V) internal pull-up on the PWRGD pin; an external pull-up 3013 F02 resistor must be used. When the ADJ pin rises to within
Figure 2. Ceramic Capacitor DC Bias Characteristics
10% of its fi nal reference value, a delay timer is started. At the end of this delay, programmed by the value of the 40 capacitor on the CT pin, the PWRGD pin switches to a high impedance and is pulled up to a logic level by an external 20 pull-up resistor. 0 X5R To calculate the capacitor value on the CT pin, use the –20 following formula: –40 Y5V I t C CT DELAY –60 TIME = • CHANGE IN VALUE (%) V – V CT HIGH ( ) CT LOW ( ) –80 BOTH CAPACITORS ARE 16V, Figure 4 shows a block diagram of the PWRGD circuit. At 1210 CASE SIZE, 10μF –100 –50 –25 0 25 50 75 100 125 start-up, the timing capacitor is discharged and the PWRGD TEMPERATURE (°C) pin will be held low. As the output voltage increases and 3013 F03 the ADJ pin crosses the 90% threshold, the JK fl ip-fl op
Figure 3. Ceramic Capacitor Temperature Characteristics
is reset, and the 3μA current source begins to charge the 3013bfb 9
