Datasheet LTC3862 (Linear Technology) - 10
| Manufacturer | Linear Technology |
| Description | Multi-Phase Current Mode Step-Up DC/DC Controller |
| Pages / Page | 42 / 10 — pin FuncTions (SSOP/QFN/TSSOP). SENSE2+ (Pin 13/Pin 11/Pin 13):. SS (Pin … |
| Revision | C |
| File Format / Size | PDF / 1.0 Mb |
| Document Language | English |
pin FuncTions (SSOP/QFN/TSSOP). SENSE2+ (Pin 13/Pin 11/Pin 13):. SS (Pin 6/Pin 4/Pin 6):. SENSE1– (Pin 22/Pin 20/Pin 22):
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Text Version of Document
LTC3862
pin FuncTions (SSOP/QFN/TSSOP) SENSE2+ (Pin 13/Pin 11/Pin 13):
Positive Inputs to the slope compensation by 66%, and connecting it to SGND Current Comparators. The ITH pin voltage programs the decreases the normalized slope compensation by 37.5%. current comparator offset in order to set the peak current See Applications Information for more details. trip threshold. This pin is normally connected to a sense
SS (Pin 6/Pin 4/Pin 6):
Soft-Start Input. For soft-start resistor in the source of the power MOSFET. operation, connecting a capacitor from this pin to SGND
SENSE1– (Pin 22/Pin 20/Pin 22):
Negative Inputs to the will clamp the output of the error amp. An internal 5µA Current Comparators. This pin is normally connected to current source will charge the capacitor and set the rate the bottom of the sense resistor. of increase of the peak switch current of the converter.
SENSE2– (Pin 14/Pin 12/Pin 14):
Negative Inputs to the
SYNC (Pin 11/Pin 9/Pin 11):
PLL Synchronization Input. Current Comparators. This pin is normally connected to Applying an external clock between 50kHz and 650kHz the bottom of the sense resistor. will cause the operating frequency to synchronize to the
SGND (Pin 9/Pin 7/Pin 9):
Signal Ground. All feedback and clock. SYNC is pulled down by a 50k internal resistor. The soft-start connections should return to SGND. For optimum rising edge of the SYNC input waveform will align with the load regulation, the SGND pin should be kelvin connected rising edge of GATE1 in closed-loop operation. A SYNC to the PCB location between the negative terminals of the signal with an amplitude greater than 1.6V is considered output capacitors. an active high, while any signal below 0.9V is considered an active low.
SLOPE (Pin 2/Pin 24/Pin 2):
This pin programs the gain of the internal slope compensation. Floating this pin
VIN (Pin 20/Pin 18/Pin 20):
Main Supply Input. A low ESR provides a normalized slope compensation gain of 1.00. ceramic capacitor should be connected between this pin Connecting this pin to 3V8 increases the normalized and SGND. 3862fc 10 For more information www.linear.com/LTC3862 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Functional Diagram Operation Applications Information Typical Applications Package Description Revision History Typical Application Related Parts
pin FuncTions (SSOP/QFN/TSSOP) SENSE2+ (Pin 13/Pin 11/Pin 13):
Positive Inputs to the slope compensation by 66%, and connecting it to SGND Current Comparators. The ITH pin voltage programs the decreases the normalized slope compensation by 37.5%. current comparator offset in order to set the peak current See Applications Information for more details. trip threshold. This pin is normally connected to a sense
SS (Pin 6/Pin 4/Pin 6):
Soft-Start Input. For soft-start resistor in the source of the power MOSFET. operation, connecting a capacitor from this pin to SGND
SENSE1– (Pin 22/Pin 20/Pin 22):
Negative Inputs to the will clamp the output of the error amp. An internal 5µA Current Comparators. This pin is normally connected to current source will charge the capacitor and set the rate the bottom of the sense resistor. of increase of the peak switch current of the converter.
SENSE2– (Pin 14/Pin 12/Pin 14):
Negative Inputs to the
SYNC (Pin 11/Pin 9/Pin 11):
PLL Synchronization Input. Current Comparators. This pin is normally connected to Applying an external clock between 50kHz and 650kHz the bottom of the sense resistor. will cause the operating frequency to synchronize to the
SGND (Pin 9/Pin 7/Pin 9):
Signal Ground. All feedback and clock. SYNC is pulled down by a 50k internal resistor. The soft-start connections should return to SGND. For optimum rising edge of the SYNC input waveform will align with the load regulation, the SGND pin should be kelvin connected rising edge of GATE1 in closed-loop operation. A SYNC to the PCB location between the negative terminals of the signal with an amplitude greater than 1.6V is considered output capacitors. an active high, while any signal below 0.9V is considered an active low.
SLOPE (Pin 2/Pin 24/Pin 2):
This pin programs the gain of the internal slope compensation. Floating this pin
VIN (Pin 20/Pin 18/Pin 20):
Main Supply Input. A low ESR provides a normalized slope compensation gain of 1.00. ceramic capacitor should be connected between this pin Connecting this pin to 3V8 increases the normalized and SGND. 3862fc 10 For more information www.linear.com/LTC3862 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Functional Diagram Operation Applications Information Typical Applications Package Description Revision History Typical Application Related Parts
